Datasheet

LTC2315-12
9
231512fa
For more information www.linear.com/LTC2315-12
TIMING DIAGRAMS
231512 TD04231512 TD03
231512 TD02231512 TD01
Hi-Z
SCK
OV
DD
/2
SDO
t
8
16TH EDGE
Hi-Z
CS
OV
DD
/2
SDO
t
9
V
OH
V
OL
SCK
OV
DD
/2
SDO
t
7
V
OH
V
OL
SCK
OV
DD
/2
SDO
t
4
Figure 1. SDO Into Hi-Z after 16TH SCK↓
Figure 3. SDO Data Valid Hold after SCK↓
Figure 2. SDO Into Hi-Z after CS↑
Figure 4. SDO Data Valid Access after SCK↓
t
THROUGHPUT
t
ACQ-MIN
t
ACQ-MIN
= 40ns
t
CONV
t
CONV
= 13.5 • t
SCK
+ t
2
+ t
10
1413124321
CS
SCK
SDO
HI-Z STATE
(MSB)
*NOTE: SDO REPRESENTS THE ANALOG INPUT FROM THE PREVIOUS CONVERSION
B0 0B9B10B11*0
231512 TD05
t
5
t
6
t
2
t
4
t
7
t
9
t
3
t
10
Figure 5: LTC2315-12 Serial Interface Timing Diagram (SCK Low During t
ACQ
)
BLOCK DIAGRAM
231512 BD
4
–
+
S/H
2.5V LDO
2×/4×
1.024V
BANDGAP
TIMING
LOGIC
1
6
7
8
THREE-STATE
SERIAL
OUTPUT
PORT
12-BIT SAR ADC
2
3
A
IN
REF
V
DD
OV
DD
2.2µF
GND
ANALOG
INPUT RANGE
0V TO V
REF
ANALOG SUPPLY
RANGE 2.7V TO 5.25V
DIGITAL SUPPLY
RANGE 1.71V TO 5.25V
5
2.2µF2.2µF
SDO
SCK
CS
TS8 PACKAGE
ALL CAPACITORS UNLESS
NOTED ARE HIGH QUALITY,
CERAMIC CHIP TYPE