Datasheet

LTC2315-12
12
231512fa
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APPLICATIONS INFORMATION
The following table illustrates the maximum throughput
achievable for each of the three timing patterns. Note
that in order to achieve the maximum throughput rate of
5Msps, the timing pattern where SCK is held high during
the acquisition time must be used.
Table 1: Maximum Throughput vs Timing Pattern
TIMING PATTERN MAXIMUM
THROUGHPUT
SCK high during T
ACQ
5Msps
SCK low during T
ACQ
4.86Msps
SCK continuous (t
THROUGHPUT
= 18 periods) 4.86Msps
Serial Data Output (SDO)
The SDO output is always forced into the high impedance
state while CS is high. The falling edge of CS starts the
conversion and enables SDO. The A/D conversion result
is shifted out on the SDO pin as a serial data stream with
the MSB first. The data stream consists of either one
leading zero (SCK held low during acquisition, Fig. 5) or
two leading zeros (SCK held high during acquisition, Fig.
6) followed by 12 bits of conversion data. There is 1 cycle
of conversion latency. Subsequent falling SCK edges after
the LSB is output will output zeros on the SDO pin. The
SDO output returns to the high impedance state after the
16th falling edge of SCK.
The output swing on the SDO pin is controlled by the
OV
DD
pin voltage and supports a wide operating range
from 1.71V to 5.25V independent of the V
DD
pin voltage.
Power Considerations
The LTC2315-12 provides two sets of power supply pins:
the analog 5V power supply (V
DD
) and the digital input/
output interface power supply (OV
DD
). The flexible OV
DD
supply allows the LTC2315-12 to communicate with any
digital logic operating between 1.8V and 5V, including
2.5V and 3.3V systems.
Entering Nap/Sleep Mode
Pulsing CS two times and holding SCK static places the
LTC2315-12 into nap mode. Pulsing CS four times and
holding SCK static places the LTC2315-12 into sleep
mode. In sleep mode, all bias circuitry is shut down,
including the internal bandgap and reference buffer, and
only leakage currents remain (0.8µA typical). Because
the reference buffer is externally bypassed with a large
capacitor (2.2µF), the LTC2315-12 requires a significant
wait time (1.1ms) to recharge this capacitance before an
accurate conversion can be made. In contrast, nap mode
does not power down the internal bandgap or reference
buffer allowing for a fast wake-up and accurate conversion
within one conversion clock cycle. Supply current during
nap mode is nominally 1.8mA.
Exiting Nap/Sleep Mode
Waking up the LTC2315-12 from either nap or sleep mode,
as shown in Figures 8 and 9, requires SCK to be pulsed
one time. A conversion may be started immediately fol
-
lowing nap mode as shown in Figure 8. A period of time
allowing
the reference voltage to recover must follow
waking up from
sleep mode as shown in Figure 9. The
wait
period required before initiating a conversion for the
recommended value of C
REF
of 2.2µF is 1.1ms.
Power Supply Sequencing
The LTC2315-12 does not have any specific power sup
-
ply sequencing requirements. Care should be taken to
observe the maximum voltage relationships described in
the Absolute Maximum Ratings section.