Datasheet

LTC4278
33
4278fc
In further contrast to traditional current mode switch-
ers, V
CMP
pin ripple is generally not an issue with the
LTC4269-1. The dynamic nature of the clamped feedback
amplifier forms an effective track/hold type response,
whereby the V
CMP
voltage changes during the flyback
pulse, but is then held during the subsequent switch-on
portion of the next cycle. This action naturally holds the
V
CMP
voltage stable during the current comparator sense
action (current mode switching).
Application Note 19 provides a method for empirically
tweaking frequency compensation. Basically, it involves
introducing a load current step and monitoring the
response.
Slope Compensation
The LTC4278 incorporates current slope compensation.
Slope compensation is required to ensure current loop
stability when the DC is greater than 50%. In some switching
regulators, slope compensation reduces the maximum peak
current at higher duty cycles. The LTC4278 eliminates this
problem by having circuitry that compensates for the slope
compensation so that maximum current sense voltage is
constant across all duty cycles.
Minimum Load Considerations
At light loads, the LTC4278 derived regulator goes into
forced continuous conduction mode. The primary-side
switch always turns on for a short time as set by the
t
ON(MIN)
resistor. If this produces more power than the
load requires, power will flow back into the primary dur-
ing the off period when the synchronization switch is on.
This does not produce any inherently adverse problems,
although light load efficiency is reduced.
Maximum Load Considerations
The current mode control uses the V
CMP
node voltage and
amplified sense resistor voltage as inputs to the current
comparator. When the amplified sense voltage exceeds the
V
CMP
node voltage, the primary-side switch is turned off.
In normal use, the peak switch current increases while
FB is below the internal reference. This continues until
V
CMP
reaches its 2.56V clamp. At clamp, the primary-side
MOSFET will turn off at the rated 100mV V
SENSE
level. This
repeats on the next cycle.
It is possible for the peak primary switch currents as
referred across R
SENSE
to exceed the max 100mV rating
because of the minimum switch on time blanking. If the
voltage on V
SENSE
exceeds 205mV after the minimum
turn-on time, the SFST capacitor is discharged, causing
the discharge of the V
CMP
capacitor. This then reduces
the peak current on the next cycle and will reduce overall
stress in the primary switch.
Short-Circuit Conditions
Loss of current limit is possible under certain conditions
such as an output short-circuit. If the duty cycle exhibited
by the minimum on-time is greater than the ratio of
secondary winding voltage (referred-to-primary) divided
by input voltage, then peak current is not controlled at
the nominal value. It ratchets up cycle-by-cycle to some
higher level. Expressed mathematically, the requirement
to maintain short-circuit control is:
DC
MIN
= t
ON(MIN)
• f
OSC
<
I
SC
• R
SEC
+ R
DS(ON)
(
)
V
IN
• N
SP
where:
t
ON(MIN)
is the primary-side switch minimum on-time
I
SC
is the short-circuit output current
N
SP
is the secondary-to-primary turns ratio (N
SEC
/N
PRI
)
(other variables as previously defined)
Trouble is typically encountered only in applications with
a relatively high product of input voltage times secondary
to primary turns ratio and/or a relatively long minimum
switch on time. Additionally, several real world effects such
as transformer leakage inductance, AC winding losses and
output switch voltage drop combine to make this simple
theoretical calculation a conservative estimate. Prudent
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