Datasheet

LTC4278
31
4278fc
between the primary-side switch and secondary-side syn-
chronous switch(es) and the subsequent current spike in
the transformer. This spike will cause additional component
stress and a loss in regulator efficiency.
The primary gate delay resistor is set with the following
equation:
R
PGDLY
kW
( )
=
t
PGDLY
ns
( )
+ 47
9.01
A good starting point is 15k.
Soft-Start Function
The LTC4278 contains an optional soft-start function that
is enabled by connecting an external capacitor between
the SFST pin and ground. Internal circuitry prevents the
control voltage at the V
CMP
pin from exceeding that on
the SFST pin. There is an initial pull-up circuit to quickly
bring the SFST voltage to approximately 0.8V. From there it
charges to approximately 2.8V with a 20µA current source.
The SFST node is discharged to 0.8V when a fault occurs.
A fault occurs when the current sense voltage is greater
than 200mV or the IC’s thermal (overtemperature) shut-
down is tripped. When SFST discharges, the V
CMP
node
voltage is also pulled low to below the minimum current
voltage. Once discharged and the fault removed, the
SFST charges up again. In this manner, switch currents
are reduced and the stresses in the converter are reduced
during fault conditions.
The time it takes to fully charge soft-start is:
t
ss
=
C
SFST
• 1.4V
20µA
= 70kW • C
SFST
µF
( )
Switcher’s UVLO Pin Function
The UVLO pin provides a user programming undervoltage
lockout. This is typically used to provide undervoltage
lockout based on V
IN
. The gate drivers are disabled when
UVLO is below the 1.24V UVLO threshold. An external
resistive divider between the input supply and ground is
used to set the turn-on voltage.
The bias current on this pin depends on the pin volt-
age and UVLO state. The change provides the user with
adjustable UVLO hysteresis. When the pin rises above
the UVLO threshold a small current is sourced out of the
pin, increasing the voltage on the pin. As the pin voltage
drops below this threshold, the current is stopped, further
dropping the voltage on UVLO. In this manner, hysteresis
is produced.
Referring to Figure 13, the voltage hysteresis at V
IN
is
equal to the change in bias current times R
A
. The design
procedure is to select the desired V
IN
referred voltage
hysteresis, V
UVHYS
. Then:
R
A
=
V
UVHYS
I
UVLO
where:
I
UVLO
= I
UVLOL
– I
UVLOH
is approximately 3.4µA
R
B
is then selected with the desired turn-on voltage:
R
B
=
R
A
V
IN(ON)
V
UVLO
– 1






APPLICATIONS INFORMATION
V
IN
R
A
LTC4278
(13a) UV Turning On
UVLO
I
UVLO
R
B
V
IN
R
A
LTC4278
(13b) UV Turning Off (13c) UV Filtering
UVLO
UVLO
R
B
V
IN
R
A2
R
A1
C
UVLO
R
B
4278 F13
I
UVLO
Figure 13. UVLO Pin Function and Recommended Filtering