LTC4278 IEEE 802.3at PD with Synchronous No-Opto Flyback Controller and 12V Aux Support DESCRIPTION FEATURES n n n n n n n n n n n n n 25.5W IEEE 802.3at Compliant (Type 2) PD 10V to 57V Auxiliary Power Input Shutdown Pin for Flexible Auxiliary Power Support Integrated State-of-the-Art No-Opto Synchronous Flyback Controller – Isolated Power Supply Efficiency >92% – 88% Efficiency Including Diode Bridge and Hot Swap™ FET Superior EMI Performance Robust 100V 0.7Ω (Typ) Integrated Hot Swap MOSFET IEEE 802.
LTC4278 ABSOLUTE MAXIMUM RATINGS PIN CONFIGURATION (Notes 1, 2) TOP VIEW Pins with Respect to VPORTN VPORTP Voltage.......................................... –0.3V to 100V VNEG Voltage.......................................... –0.3V to VPORTP VNEG Pull-Up Current...................................................1A SHDN........................................................ –0.3V to 100V RCLASS, Voltage............................................. –0.3V to 7V RCLASS Source Current.......................
LTC4278 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. PARAMETER CONDITIONS MIN TYP MAX UNITS 60 9.8 21 37.2 V V V V V V Interface Controller (Note 4) Operating Input Voltage Signature Range Classification Range ON Voltage OFF Voltage Overvoltage Lockout At VPORTP (Note 5) l l l l 1.5 12.5 30.0 71 ON/OFF Hysteresis Window l 4.1 V Signature/Class Hysteresis Window l 1.
LTC4278 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. PARAMETER CONDITIONS MIN TYP MAX UNITS PWM Controller (Note 10) Power Supply VCC Operating Range l 4.5 4 VCC Supply Current (ICC) VCMP = Open (Note 11) l VCC Shutdown Current VCMP = Open, VUVLO = 0V l 20 V 6.4 10 mA 50 150 µA 1.237 1.
LTC4278 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. PARAMETER CONDITIONS MIN TYP MAX UNITS Load Compensation Load Compensation to VSENSE Offset Voltage VRCMP with VSENSE+ = 0V 0.8 mV Feedback Pin Load Compensation Current VSENSE+ = 20mV, VFB = 1.230V 20 µA UVLO Function UVLO Pin Threshold (VUVLO) UVLO Pin Bias Current l VUVLO = 1.2V VUVLO = 1.
LTC4278 TYPICAL PERFORMANCE CHARACTERISTICS Input Current vs Input Voltage 25k Detection Range Input Current vs Input Voltage 50 TA = 25°C VPORTP CURRENT (mA) VPORTP CURRENT (mA) TA = 25°C 0.3 0.2 30 CLASS 3 20 CLASS 2 0.1 10 0 0 0 2 4 6 VPORTP VOLTAGE (V) 8 10 CLASS 1 OPERATION CLASS 4 40 0.4 Input Current vs Input Voltage 11.0 VPORTP CURRENT (mA) 0.5 CLASS 1 CLASS 0 0 4278 G01 10 50 20 30 40 VPORTP VOLTAGE (V) (RISING) 10.5 85°C –40°C 10.0 9.
LTC4278 TYPICAL PERFORMANCE CHARACTERISTICS VCC Shutdown Current vs Temperature VCC Current vs Temperature VUVLO = 0 80 70 108 DYNAMIC CURRENT CPG = 1nF, CSG = 1nF, fOSC = 100kHz 106 8 VCC = 14V 7 IVCC (mA) VCC CURRENT (µA) 110 9 60 SENSE Voltage vs Temperature 10 50 40 SENSE VOLTAGE (mV) 90 6 30 STATIC PART CURRENT 5 20 0 –50 –25 50 25 75 0 TEMPERATURE (°C) 100 VCC = 14V 3 50 –50 –25 25 75 0 TEMPERATURE (°C) 125 SENSE Fault Voltage vs Temperature 110 98 96 92 100 90 –50 125
LTC4278 TYPICAL PERFORMANCE CHARACTERISTICS Feedback Amplifier Source and Sink Current vs Temperature 1600 1550 1050 1500 1450 gm (µmho) IVCMP (µA) 1650 SINK CURRENT VFB = 1.4V 60 1700 1100 SOURCE CURRENT VFB = 1.
LTC4278 TYPICAL PERFORMANCE CHARACTERISTICS Minimum PG On-Time vs Temperature 325 300 RtON(MIN) = 158k 330 250 tPGDLY (ns) tON(MIN) (ns) 200 310 300 290 RENDLY = 90k 305 RPGDLY = 27.4k 320 285 tENDLY (ns) 340 Enable Delay Time vs Temperature PG Delay Time vs Temperature 150 RPGDLY = 16.
LTC4278 PIN FUNCTIONS SHDN (Pin 1): Shutdown Input. Use this pin for auxiliary power application. Drive SHDN high to disable LTC4278 operation and corrupt the signature resistance. If unused, tie SHDN to VPORTN. T2P (Pin 2): Type 2 PSE Indicator, Open-Drain. Low impedance indicates the presence of a Type 2 PSE. RCLASS (Pin 3): Class Select Input. Connect a resistor between RCLASS and VPORTN to set the classification load current (see Table 2). NC (Pins 4, 7, 8, 25, 28, 31): No Connect.
LTC4278 PIN FUNCTIONS Information section for details. This pin is used for the UVLO function of the switching regulator. The PD interface section has an internal UVLO. SENSE –, SENSE+ (Pins 19, 20): Current Sense Inputs. These pins are used to measure primary-side switch current through an external sense resistor. Peak primary-side current is used in the converter control loop. Make Kelvin connections to the sense resistor RSENSE to reduce noise problems. SENSE – connects to the GND side.
LTC4278 BLOCK DIAGRAM CLASSIFICATION CURRENT LOAD 1 2 3 SHDN VPORTP + 1.237V 16k T2P 32 25k – RCLASS NC PWRGD 31 30 CONTROL CIRCUITS PWRGD 4 NC 5 6 VPORTN 29 14V VNEG VPORTN VNEG BOLD LINE INDICATES HIGH CURRENT PATH 7 NC 27 26 8 NC VCC CLAMPS 0.7 – 1.237V REFERENCE (VFB) INTERNAL REGULATOR + VCMP + S Q R Q UVLO + TSD SFST 1V 14 OVERCURRENT FAULT – CURRENT COMPARATOR IUVLO 17 COLLAPSE DETECT – – UVLO 16 ERROR AMP + – 18 – 3V DISABLE 0.8V FB 1.
LTC4278 APPLICATIONS INFORMATION OVERVIEW 50 Power over Ethernet (PoE) continues to gain popularity as more products are taking advantage of having DC power and high speed data available from a single RJ45 connector. As PoE continues to grow in the marketplace, powered device (PD) equipment vendors are running into the 12.95W power limit established by the IEEE 802.3af standard. VPORTP (V) 40 30 ON 10 CLASSIFICATION DETECTION V2 DETECTION V1 VPORTP – VNEG (V) 50 The IEE802.
LTC4278 APPLICATIONS INFORMATION The input diode bridge introduces a voltage drop that affects the range for each mode of operation. The LTC4278 compensates for these voltage drops so that a PD built with the LTC4278 meets the IEEE 802.3af/IEEE 802.3at-established voltage ranges. Note the Electrical Characteristics are referenced with respect to the LTC4278 package pins. Table 1. LTC4278 Modes of Operation as a Function of Input Voltage VPORTP–VPORTN (V) LTC4278 MODES OF OPERATION 0V to 1.
LTC4278 APPLICATIONS INFORMATION SIGNATURE CORRUPT OPTION In some designs that include an auxiliary power option, it is necessary to prevent a PD from being detected by a PSE. The LTC4278 signature resistance can be corrupted with the SHDN pin (Figure 3). Taking the SHDN pin high will reduce the signature resistor below 11k which is an invalid signature per the IEEE 802.3af/IEEE 802.3at specification, and alerts the PSE not to apply power.
LTC4278 APPLICATIONS INFORMATION SIGNATURE CORRUPT DURING MARK 50 VPORTP (V) 40 30 1st CLASS 2nd CLASS ON OFF 20 10 DETECTION V1 DETECTION V2 1st MARK 2nd MARK PD CURRENT INRUSH LOAD, ILOAD 1st CLASS 2nd CLASS 40mA PD STABILITY DURING CLASSIFICATION TIME DETECTION V1 DETECTION V2 VPORTP – VNEG (V) 50 40 1st MARK 2nd MARK dV = INRUSH dt C1 30 OFF ON 20 OFF τ = RLOAD C1 10 VPORTP – T2P (V) TIME –20 –30 –40 TRACKS VPORTN –50 INRUSH = 100mA RCLASS = 30.
LTC4278 APPLICATIONS INFORMATION To control the power-on surge currents in the system, the LTC4278 provides a fixed inrush current, allowing C1 to ramp up to the line voltage in a controlled manner. is disconnected, and classification mode resumes. C1 discharges through the LTC4278 circuitry. The LTC4278 keeps the PD inrush current below the PSE current limit to provide a well controlled power-up characteristic that is independent of the PSE behavior.
LTC4278 APPLICATIONS INFORMATION PWRGD PIN WHEN SHDN IS INVOKED In PD applications where an auxiliary power supply invokes the SHDN feature, the PWRGD pin becomes high impedance. This prevents the PWRGD pin that is connected to the UVLO pin from interfering with the DC/DC converter operations when powered by an auxiliary power supply. OVERVOLTAGE LOCKOUT The LTC4278 includes an overvoltage lockout (OVLO) feature (Figure 6) which protects the LTC4278 and its load from an overvoltage event.
LTC4278 APPLICATIONS INFORMATION An input diode bridge must be rated above the maximum current the PD application will encounter at the temperature the PD will operate. Diode bridge vendors typically call out the operating current at room temperature, but derate the maximum current with increasing temperature. Consult the diode bridge vendors for the operating current derating curve.
LTC4278 APPLICATIONS INFORMATION Classification Resistor (RCLASS) The RCLASS resistor sets the classification load current, corresponding to the PD power classification. Select the value of RCLASS from Table 2 and connect the resistor between the RCLASS and VPORTN pins as shown in Figure 4, or float the RCLASS pin if the classification load current is not required. The resistor tolerance must be 1% or better to avoid degrading the overall accuracy of the classification circuit.
LTC4278 APPLICATIONS INFORMATION for PoE dominance. Furthermore, PD applications may also opt for a seamless transition — that is, without power disruption — between PoE and auxiliary power. The most common auxiliary power option injects power at VNEG. Figure 9 presents an example of this application. In this example, the auxiliary port injects 48V onto the line via diode D1.
LTC4278 APPLICATIONS INFORMATION compensation circuitry. The logic block also contains circuitry to control the special dynamic requirements of flyback control. For more information on the basics of current mode switcher/controllers and isolated flyback converters see Application Note 19. Feedback Amplifier—Pseudo DC Theory For the following discussion, refer to the simplified Switching Regulator Feedback Amplifier diagram (Figure 10A).
LTC4278 APPLICATIONS INFORMATION T1 VFLBK FLYBACK LTC4278 FEEDBACK AMP R1 FB – 1V R2 VFB 1.237V + 16 • VCMP + 17 CVCMP VIN PRIMARY • SECONDARY • + COUT ISOLATED OUTPUT MP – COLLAPSE DETECT MS R ENABLE S Q 4278 F10a Figure 10a. LTC4278 Switching Regulator Feedback Amplifier PRIMARY-SIDE MOSFET DRAIN VOLTAGE VFLBK 0.8 • VFLBK VIN PG VOLTAGE SG VOLTAGE tON(MIN) ENABLE DELAY MIN ENABLE PG DELAY 4278 F10b FEEDBACK AMPLIFIER ENABLED Figure 10b.
LTC4278 APPLICATIONS INFORMATION to transformer leakage inductance. The latter causes a voltage spike on the primary side, not directly related to output voltage. Some time is also required for internal settling of the feedback amplifier circuitry. In order to maintain immunity to these phenomena, a fixed delay is introduced between the switch turn-off command and the enabling of the feedback amplifier. This is termed “enable delay.
LTC4278 APPLICATIONS INFORMATION Assuming relatively fixed power supply efficiency, Eff, power balance gives: POUT = Eff • PIN K1• VOUT • IOUT = Eff • VIN • IIN Average primary-side current is expressed in terms of output current as follows: IIN = K1•IOUT VOUT VIN • Eff Transformer design/specification is the most critical part of a successful application of the LTC4278. The following sections provide basic information about designing the transformer and potential tradeoffs.
LTC4278 APPLICATIONS INFORMATION Note the use of the external feedback resistive divider ratio to set output voltage provides the user additional freedom in selecting a suitable transformer turns ratio. Turns ratios that are the simple ratios of small integers; e.g., 1:1, 2:1, 3:2 help facilitate transformer construction and improve performance.
LTC4278 APPLICATIONS INFORMATION A final note—the susceptibility of the system to bistable behavior is somewhat a function of the load current/ voltage characteristics. A load with resistive—i.e., I = V/R behavior—is the most apt to be bistable. Capacitive loads that exhibit I = V2/R behavior are less susceptible. Secondary Leakage Inductance Leakage inductance on the secondary forms an inductive divider on the transformer secondary, reducing the size of the flyback pulse.
LTC4278 APPLICATIONS INFORMATION when the peak design current is exceeded. This results in an abrupt increase in inductor ripple current and, consequently, output voltage ripple. Do not allow the core to saturate! The maximum peak primary current occurs at minimum VIN: PIN VIN(MIN) • DCMAX IPK = X • 1+ MIN 2 1+ XMIN 1 = N • VIN(MIN) It is recommended that the Thevenin impedance of the resistive divider (R1||R2) is roughly 3k for bias current cancellation and other reasons. 1 = 49.
LTC4278 APPLICATIONS INFORMATION Selecting the Load Compensation Resistor 4. Compute: The expression for RCMP was derived in the Operation section as: R • (1– DC) RCMP = K1• SENSE • R1• NSF ESR + RDS(ON) 6. Disconnect the ground short to CCMP and connect a 0.1µF filter capacitor to ground. Measure the output impedance RS(OUT) = DVOUT/DIOUT with the new compensation in place. RS(OUT) should have decreased significantly. Fine tuning is accomplished experimentally by slightly altering RCMP.
LTC4278 APPLICATIONS INFORMATION trace length and area to minimize stray capacitance and potential noise pick-up. You can synchronize the oscillator frequency to an external frequency. This is done with a signal on the SYNC pin. Set the LTC4278 frequency 10% slower than the desired external frequency using the OSC pin capacitor, then use a pulse on the SYNC pin of amplitude greater than 2V and with the desired frequency.
LTC4278 APPLICATIONS INFORMATION between the primary-side switch and secondary-side synchronous switch(es) and the subsequent current spike in the transformer. This spike will cause additional component stress and a loss in regulator efficiency. The primary gate delay resistor is set with the following equation: RPGDLY (kW) = tPGDLY (ns) + 47 9.01 A good starting point is 15k.
LTC4278 APPLICATIONS INFORMATION If we wanted a VIN-referred trip point of 36V, with 1.8V (5%) of hysteresis (on at 36V, off at 34.2V): R A = 1.8V = 529k, use 523k 3.4µA RB = 523k = 18.5k, use 18.7 k 36V – 1 1.23V Even with good board layout, board noise may cause problems with UVLO. You can filter the divider but keep large capacitance off the UVLO node because it will slow the hysteresis produced from the change in bias current.
LTC4278 APPLICATIONS INFORMATION In further contrast to traditional current mode switchers, VCMP pin ripple is generally not an issue with the LTC4269‑1. The dynamic nature of the clamped feedback amplifier forms an effective track/hold type response, whereby the VCMP voltage changes during the flyback pulse, but is then held during the subsequent switch-on portion of the next cycle. This action naturally holds the VCMP voltage stable during the current comparator sense action (current mode switching).
LTC4278 APPLICATIONS INFORMATION design evaluates the switcher for short-circuit protection and adds any additional circuitry to prevent destruction. Output Voltage Error Sources The LTC4278’s feedback sensing introduces additional minor sources of errors. The following is a summary list: • The internal bandgap voltage reference sets the reference voltage for the feedback amplifier. The specifications detail its variation. • The external feedback resistive divider ratio directly affects regulated voltage.
LTC4278 APPLICATIONS INFORMATION CMILLER is calculated from the gate charge curve included on most MOSFET data sheets (Figure 16). PDIS(SEC) = IRMS(SEC)2 • RDS(ON)(1 + d) MILLER EFFECT VGS a b QA QB GATE CHARGE (QG) 4278 F16 Figure 16. Gate Charge Curve The flat portion of the curve is the result of the Miller (gate to-drain) capacitance as the drain voltage drops.
LTC4278 APPLICATIONS INFORMATION Capacitor Selection In a flyback converter, the input and output current flows in pulses, placing severe demands on the input and output filter capacitors. The input and output filter capacitors are selected based on RMS current ratings and ripple voltage. Select an input capacitor with a ripple current rating greater than: IRMS(PRI) = PIN 1– DCMAX DCMAX VIN(MIN) Continuing the example: IRMS(PRI) = 29.5W 41V 1– 49.4% = 0.728A 49.
LTC4278 APPLICATIONS INFORMATION One way to reduce cost and improve output ripple is to use a simple LC filter. Figure 18 shows an example of the filter. L1, 0.1µH FROM SECONDARY WINDING + C1 47µF ×3 + ISOLATION VOUT COUT 470µF unidirectional 58V transient voltage suppressor be installed between the diode bridge and the LTC4278 (D3 in Figure 2). COUT2 1µF RLOAD 4278 F18 Figure 18. The design of the filter is beyond the scope of this data sheet.
LTC4278 APPLICATIONS INFORMATION current will flow through the parasitic body diode of the internal MOSFET and may cause permanent damage to the LTC4278. Check that the maximum BVDSS ratings of the MOSFETs are not exceeded due to inductive ringing. This is done by viewing the MOSFET node voltages with an oscilloscope. If it is breaking down, either choose a higher voltage device, add a snubber or specify an avalanche-rated MOSFET.
AUX– SPARE2 VPORT_N SPARE1 RXCT TXCT VPORT_P AUX+ AUXILIARY SUPPLY 8V TO 57V B1100 (8 PLCS) S1B L1: COILCRAFT, DO1813P-181HC L2: WÜRTH, 7443330820 C2, C6: TDK, C3225X7S2A335M C1, C3: MURATA, GRM31CR60J226KE19 C9: TDK, C3225X5R0J107M 20k 2.49k 54.9k 294k 0.1µF 100V 10Ω PDS5100H 24k BSS63LT1 SMAJ58A + 3.01k 21.5k VPORTP T2P B1100 30.9Ω RCLASS VPORTN VPORTN UVLO SHDN NC FB C6 C2 3.3µF ×2 PWRGD /PWRGD 10µF 100V L2 8.2µH LTC4278IDKD 1µF VCC FMMT624 VCC 7.
LTC4278 PACKAGE DESCRIPTION Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. DKD Package DKD Package 32-Lead Plastic DFN (7mm × 4mm) 32-Lead Plastic DFN (7mm × 4mm) (Reference LTC DWG # 05-08-1734 Rev A) (Reference LTC DWG # 05-08-1734 Rev A) 0.70 ±0.05 0.70 ±0.05 4.50 ±0.05 6.43 ±0.05 4.50 ±0.05 6.43 ±0.05 2.65 ±0.05 2.65 ±0.05 3.103.10 ±0.05 ±0.05 PACKAGE PACKAGE OUTLINE OUTLINE 0.20 ±0.05 0.20 0.40 BSC 0.40 BSC 6.00REF REF 6.
LTC4278 REVISION HISTORY (Revision history begins at Rev B) REV DATE DESCRIPTION B 3/12 Added B1100 to schematic C 4/12 PAGE NUMBER 1, 19 Revised Max Junction Temperature 2 Added Typical Application 39 Updated component values on Typical Application 1 Updated Maximum Junction Temperature to 125°C 2 Updated Typical Application 39 4278fc Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use.
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