Datasheet

LTM8048
13
8048ff
For more information www.linear.com/LTM8048
APPLICATIONS INFORMATION
PCB Layout
Most of the headaches associated with PCB layout have
been alleviated or even eliminated by the high level of
integration of the LTM8048. The LTM8048 is neverthe
-
less a switching power supply, and care must be taken to
minimize electrical noise to ensure proper operation. Even
with the high level of integration, you may fail to achieve
specified operation with a haphazard or poor layout. See
Figure 1 for a
suggested layout. Ensure that the grounding
and heat sinking are acceptable.
5. Connect all of the GND connections to as large a copper
pour or plane area as possible on the top layer. Avoid
breaking the ground connection between the external
components and the LTM8048.
6. Use vias to connect the GND copper area to the board’s
internal ground planes. Liberally distribute these GND
vias to provide both a good ground connection and
thermal path to the internal planes of the printed circuit
board. Pay attention to the location and density of the
thermal vias in Figure 1. The LTM8048 can benefit from
the heat sinking afforded by vias that connect to internal
GND planes at these locations, due to their proximity
to internal power handling components. The optimum
number of thermal vias depends upon the printed
circuit board design. For example, a board might use
very small via holes. It should employ more thermal
vias than a board that uses larger holes.
Hot-Plugging Safely
The small size, robustness and low impedance of ceramic
capacitors make them an attractive option for the input
bypass capacitor of the LTM8048. However, these capaci
-
tors can cause problems if the LTM8048 is plugged into a
live
supply
(see Linear Technology Application Note 88 for
a complete discussion). The low loss ceramic capacitor
combined with stray inductance in series with the power
source forms an underdamped tank circuit, and the volt
-
age at the V
IN
pin of the LTM8048 can ring to more than
twice the nominal input voltage, possibly exceeding the
LTM8048’s rating and damaging the part. A similar phe
-
nomenon can occur inside the LTM8048 module, at the
output of the integrated EMI filter, with the same potential
of damaging the part. If the input supply is poorly con
-
trolled or the user will be plugging the LTM8048 into an
energized supply, the input network should be designed
to prevent this overshoot. This can be accomplished by
installing a small resistor in series to V
IN
, but the most
popular method of controlling input voltage overshoot is
adding an electrolytic bulk capacitor to the V
IN
or f
IN
net.
This capacitor’s relatively high equivalent series resistance
damps the circuit and eliminates the voltage overshoot.
The extra capacitor improves low frequency ripple filter
-
ing and can slightly improve the efficiency of the circuit,
though it can be a large component in the circuit.
Figure 1. Layout Showing Suggested External Components,
Planes and Thermal Vias
8048 F01
BIAS
RUN
GND
ADJ2 BYP
ADJ1
LTM8048
SS
C
OUT2
C
OUT1
V
OUT
–
V
OUT2
V
IN
V
OUT1
C
IN
THERMAL/INTERCONNECT VIAS
A few rules to keep in mind are:
1. Place the R
ADJ1
and R
ADJ2
resistors as close as possible
to their respective pins.
2. Place the C
IN
capacitor as close as possible to the V
IN
and GND connections of the LTM8048.
3. Place the C
OUT1
capacitor as close as possible to V
OUT1
and V
OUT
–
. Likewise, place the C
OUT2
capacitor as close
as possible to V
OUT2
and V
OUT
–
.
4. Place the C
IN
and C
OUT
capacitors such that their
ground current flow directly adjacent or underneath
the LTM8048.