Datasheet

LTC2754
8
2754f
PIN FUNCTIONS
GE
ADJA
(Pin1): Gain Adjust Pin for DAC A. This control
pin can be used to null gain error or to compensate for
reference errors. Nominal adjustment range is ±512 LSB
(LTC2754-16) for a voltage input range of ±V
RINA
(i.e., ±5V
for a 5V reference input). Tie to ground if not used.
R
INA
(Pin 2): Input Resistor for Reference Inverting
Amplifi er. The 20k input resistor is connected internally
from R
INA
to R
COMA
. For normal operation tie R
INA
to the
external reference voltage V
REFA
(see Typical Applications).
Any or all of these precision-matched resistor sets (Each
set comprising R
INX
, R
COMX
and REFX) may be used to
invert one or more positive reference voltages to the nega-
tive voltages needed by the DACs. Typically 5V; accepts
up to ±15V.
I
OUT2A
(Pin 3): DAC A Current Output Complement. Tie
I
OUT2A
to ground.
GND (Pin 4): Ground; provides shielding for I
OUT2A
. Tie
to ground.
CS/LD (Pin 5): Synchronous Chip Select and Load Pin.
SDI (Pin 6): Serial Data Input. Data is clocked in on the
rising edge of the serial clock (SCK) when CS/LD is low.
SCK (Pin 7): Serial Clock.
SRO (Pin 8): Serial Readback Output. Data is clocked out
on the falling edge of SCK. Readback data begins clocking
out after the last address bit A0 is clocked in. SRO is an
active output only when the chip is selected (i.e., when
CS/LD is low). Otherwise SRO presents a high-impedance
output in order to allow other parts to control the bus.
SROGND (Pin 9): Ground pin for SRO. Tie to ground.
V
DD
(Pin 10): Positive Supply Input; 2.7V ≤ V
DD
≤ 5.5V. By-
pass with a 0.1F low-ESR ceramic capacitor to ground.
GND (Pin 11): Ground. Tie to ground.
I
OUT2D
(Pin 12): DAC D Current Output Complement. Tie
I
OUT2D
to ground.
R
IND
(Pin 13): Input Resistor for Reference Inverting
Amplifi er. The 20k input resistor is connected inter-
nally from R
IND
to R
COMD
. For normal operation tie R
IND
to the external reference voltage V
REFD
(see Typical
Applications). Any or all of these precision-matched resis-
tor sets (Each set comprising R
INX
, R
COMX
and REFX) may
be used to invert one or more positive reference voltages
to the negative voltages needed by the DACs. Typically
5V; accepts up to ±15V.
GE
ADJD
(Pin 14): Gain Adjust Pin for DAC D. This control
pin can be used to null gain error or to compensate for
reference errors. Nominal adjustment range is ±512 LSB
(LTC2754-16) for a voltage input range of ±V
RIND
(i.e., ±5V
for a 5V reference input). Tie to ground if not used.
R
COMD
(Pin 15): Center Tap Point for Reference Amplifi er
Inverting Resistors. The 20k reference inverting resistors
are connected internally from R
IND
to R
COMD
and from
R
COMD
to REFD, respectively (see Block Diagram). For
normal operation tie R
COMD
to the negative input of external
reference inverting amplifi er (see Typical Applications).
REFD (Pin 16): Inverted Reference Voltage for DAC D, with
internal connection to the reference inverting resistor. The
20k resistor is connected internally from REFD to R
COMD
.
For normal operation tie this pin to the output of reference
inverting amplifi er (see Typical Applications). Typically –5V;
accepts up to ±15V. The impedance looking into this pin
is 10k to ground (R
IND
and R
COMD
fl oating).
R
OFSD
(Pin 17): Bipolar Offset Network for DAC D. This
pin provides the translation of the output voltage range for
bipolar spans. Accepts up to ±15V; for normal operation
tie to the positive reference voltage at R
IND
(Pin 13). The
impedance looking into this pin is 20k to ground.
R
FBD
(Pin 18): DAC D Feedback Resistor. For normal
operation tie to the output of the I/V converter amplifi er
for DAC D (see Typical Applications). The DAC output
current from I
OUT1D
fl ows through the feedback resistor
to the R
FBD
pin. The impedance looking into this pin is
10k to ground.
I
OUT1D
(Pin 19): DAC D Current Output. This pin is a
virtual ground when the DAC is operating and should
reside at 0V. For normal operation tie to the negative
input of the I/V converter amplifi er for DAC D (see Typi-
cal Applications).