Datasheet

LTC2657
9
2657f
TIMING CHARACTERISTICS
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All voltages are with respect to GND.
Note 3: Linearity and monotonicity are defi ned from code kL to code
2
N
– 1, where N is the resolution and kL is the lower end code for which
no output limiting occurs. For V
REF
= 2.5V and N = 16, kL = 128 and
linearity is defi ned from code 128 to code 65535. For V
REF
= 2.5V and
N = 12, kL = 8 and linearity is defi ned from code 8 to code 4,095.
Note 4: Inferred from measurement at code 128 (LTC2657-16) or code 8
(LTC2657-12).
Note 5: DC crosstalk is measured with V
CC
= 5V and using internal
reference with the measured DAC at mid-scale.
Note 6: This IC includes current limiting that is intended to protect the
device during momentary overload conditions. Junction temperature can
exceed the rated maximum during current limiting. Continuous operation
above the specifi ed maximum operating junction temperature may impair
device reliability.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
V
CC
= 2.7V to 5.5V
f
SCL
SCL Clock Frequency
l
0 400 kHz
t
HD(STA)
Hold Time (Repeated) Start Condition
l
0.6 µs
t
LOW
Low Period of the SCL Clock Pin
l
1.3 µs
t
HIGH
High Period of the SCL Clock Pin
l
0.6 µs
t
SU(STA)
Set-Up Time for a Repeated Start Program
l
0.6 µs
t
HD(DAT)
Data Hold Time
l
0 0.9 µs
t
SU(DAT)
Data Set-Up Time
l
100 ns
t
r
Rise Time of Both SDA and SCL Signals
l
20+0.1C
B
300 ns
t
f
Fall Time of Both SDA and SCL Signals
l
20+0.1C
B
300 ns
t
SU(STO)
Set-Up Time for Stop Condition
l
0.6 µs
t
BUF
Bus Free Time Between a Stop and Start Condition
l
1.3 µs
t
1
Falling edge of the 9th Clock of the 3rd Input Byte
to LDAC High or Low Transition
l
400 ns
t
2
LDAC Low Pulse Width
l
20 ns
The l denotes the specifi cations which apply over the full operating temperature
range, otherwise specifi cations are at T
A
= 25°C. LTC2657B-L16/LTC2657-L12/LTC2657B-H16/LTC2657-H12 (see Figure 1).
Note 7: Temperature coeffi cient is calculated by dividing the maximum
change in output voltage by the specifi ed temperature range.
Note 8: Digital inputs at 0V or V
CC
.
Note 9: Guaranteed by design and not production tested.
Note 10: Internal reference mode. DAC is stepped 1/4 scale to 3/4 scale
and 3/4 scale to 1/4 scale. Load is 2k in parallel with 200pF to GND.
Note 11: V
CC
= 5V (H-Options) or V
CC
= 3V (L-Options), internal reference
mode. DAC is stepped ±1LSB between half-scale and half-scale –1. Load is
2k in parallel with 200pF to GND.
Note 12: DAC-to-DAC crosstalk is the glitch that appears at the output
of one DAC due to a full-scale change at the output of another DAC. It is
measured with V
CC
= 5V, using internal reference, with the measured DAC
at mid-scale.
Note 13: C
B
= capacitance of one bus line in pF.
Note 14: Gain error specifi cation may be degraded for reference input
voltages less than 1V. See Gain Error vs Reference Input curve in the
Typical Performance Characteristics section.