Datasheet
LTC2657
15
2657f
PIN FUNCTIONS
V
OUTA
to V
OUTH
(Pins 1, 3, 4, 13, 14, 15, 16, 20/Pins 2,
3, 5, 6, 15, 16, 17, 18): DAC Analog Voltage Outputs.
The output range is 0V to 2 times the voltage at the
REFIN/OUT pin.
REFCOMP (Pin 2/Pin 4): Internal Ref erence Compensation
pin. For low noise and reference stability, tie 0.1µF cap
to GND. Connect to GND to use an external reference
at start-up. Command 0111b must still be issued to
turn off internal reference.
REFIN/OUT (Pin 5/Pin 7): This pin acts as the Internal
Reference output in Internal Reference mode and acts
as the Reference Input pin in External Reference mode.
When acting as an output the nominal voltage at this
pin is 1.25V for-L Options and 2.048V for-H Options.
For low noise and reference stability tie a capacitor
to GND. Capacitor value must be <= C
REFCOMP
.
In External Reference mode, the allowable reference
input voltage range is 0.5V to
V
CC
/2
.
LDAC (Pin 6/Pin 8): Asynchronous DAC Update Pin.
A falling edge on this input after four bytes have been
written into the part immediately updates the DAC
register with the contents of the input register. A low
on this input without a complete 32-bit (four bytes
including the slave address) data write transfer to the
part does not update the DAC output. Software power-
down is disabled when LDAC is low.
CA2 (Pin 9/Pin 7): Chip Address Bit 2. Tie this pin
to V
CC
, GND or leave it fl oating to select an I
2
C slave
address for the part (See Table 2).
SCL (Pin 8/Pin 10): Serial Clock Input Pin. Data is
shifted into the SDA pin at the rising edges of the clock.
This high impedance pin requires a pull-up resistor or
current source to V
CC
.
SDA (Pin 9/Pin 11 ): Serial Data Bidi rectional Pin. Data
is shifted into the SDA pin and acknowledged by the
SDA pin. This is a high impedance pin while data is
shifted in. It is an open-drain N-channel output during
acknowledgement. This pin requires a pull-up resistor
or current source to V
CC
.
CA1 (Pin 10/Pin 12): Chip Address Bit 1. Tie this pin
to V
CC
, GND or leave it fl oating to select an I
2
C slave
address for the part (See Table 2)
CA0 (Pin 11/Pin 13): Chip Address Bit 0. Tie this pin
to V
CC
, GND or leave it fl oating to select an I
2
C slave
address for the part (See Table 2).
PORSEL (Pin 12/Pin 14): Power-On-Reset Select pin. If
tied to GND, the part resets to Zero-Scale at power up. If
tied to V
CC
, the part resets to Mid-Scale at power up.
V
CC
(Pin 17/Pin 19): Supply Voltage Input. For –L
Options, 2.7V ≤ V
CC
≤ 5.5V, and for –H Options, 4.5V
≤ V
CC
≤ 5.5V. Bypass to ground with a 0.1µF capacitor
placed as close to pin as possible.
GND (Pin 18/Pin 20): Ground.
REFLO (Pin 19/Pin 1): Reference Low pin. The voltage
at this pin sets the zero-scale voltage of all DACs. This
pin should be tied to GND.
Exposed Pad (Pin 21/Pin 21): Ground. Must be Soldered
to PCB Ground.
(QFN/TSSOP)