Datasheet

LTC2460/LTC2462
16
24602fa
applicaTions inForMaTion
noise increases. A 0.1μF capacitor should also be placed
on the COMP pin. This pin is tied to an internal point in the
reference and is used for stability. In order for the refer-
ence to remain stable the capacitor placed on the COMP
pin must be greater than or equal to the capacitor tied to
the REFOUT pin. The REFOUT pin cannot be overridden
by an external voltage. If a reference voltage greater than
1.25V is required, the LTC2450/LTC2452 should be used.
Depending on the size of the capacitors tied to the REFOUT
and COMP pins, the internal reference has a correspond-
ing start up time. This start up time is typically 12ms
when 0.1μF capacitors are used. At initial power up, the
first conversion result can be aborted or ignored. At the
completion of this first conversion, the reference has
settled and all subsequent conversions are valid.
If the reference is put to sleep (program SLP = 1 and
CS = 1) the reference is powered down after the next
conversion. This conversion result is valid. On CS falling
edge, the reference is powered up. In order to ensure the
reference output has settled before the next conversion,
the power up time can be extended by delaying the data
read 12ms after the falling edge of CS. Once all 16 bits
are read from the device or CS is brought HIGH, the next
conversion automatically begins. In the default operation,
the reference remains powered up at the conclusion of the
conversion cycle.
Driving V
IN
+
and V
IN
–
The input drive requirements can best be analyzed using
the equivalent circuit of Figure 16. The input signal V
SIG
is
connected to the ADC input pins (IN
+
and IN
–
) through an
equivalent source resistance R
S
. This resistor includes both
the actual generator source resistance and any additional
optional resistors connected to the input pins. Optional
input capacitors C
IN
are also connected to the ADC input
pins. This capacitor is placed in parallel with the ADC
input parasitic capacitance C
PAR
. Depending on the PCB
layout, C
PAR
has typical values between 2pF and 15pF. In
addition, the equivalent circuit of Figure 16 includes the
converter equivalent internal resistor R
SW
and sampling
capacitor C
EQ
.
Figure 16. LTC2460/LTC2462 Input Drive Equivalent Circuit
I
LEAK
I
LEAK
R
SW
15k
(TYP)
I
CONV
C
IN
IN
+
(LTC2462)
IN
(LTC2460)
V
CC
SIG
+
SIG
–
R
S
C
EQ
0.35pF
(TYP)
C
PAR
+
–
24602 F16
I
LEAK
I
LEAK
R
SW
15k
(TYP)
I
CONV
C
IN
IN
–
(LTC2462)
V
CC
R
S
C
EQ
0.35pF
(TYP)
C
PAR
+
–
There are some immediate trade-offs in R
S
and C
IN
without
needing a full circuit analysis. Increasing R
S
and C
IN
can
give the following benefits:
1) Due to the LTC2460/LTC2462’s input sampling algorithm,
the input current drawn by either V
IN
+
or V
IN
–
over a
conversion cycle is typically 50nA. A high R
S
• C
IN
at-
tenuates the high frequency components of the input
current, and R
S
values up to 1k result in <1LSB error.
2) The bandwidth from V
SIG
is reduced at the input pins
(IN
+
, IN
–
or IN). This bandwidth reduction isolates the
ADC from high frequency signals, and as such provides
simple antialiasing and input noise reduction.
3) Switching transients generated by the ADC are attenu-
ated before they go back to the signal source.
4) A large C
IN
gives a better AC ground at the input pins,
helping reduce reflections back to the signal source.
5) Increasing R
S
protects the ADC by limiting the current
during an outside-the-rails fault condition.