Datasheet

LTC2460/LTC2462
14
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applicaTions inForMaTion
output the sign (D15) of the result of the just completed
conversion. While a low logic level is maintained at SCK
pin and CS is subsequently pulled high (CS = HIGH) the
remaining 15 bits of the result (D14:D0) are discarded
and a new conversion cycle starts.
Following the aborted I/O, additional clock pulses in the
CONVERT state are acceptable, but excessive signal tran-
sitions on SCK can potentially create noise on the ADC
during the conversion, and thus may negatively influence
the conversion accuracy.
2-Wire Operation
The 2-wire operation modes, while reducing the number of
required control signals, should be used only if the LTC2460/
LTC2462 low power sleep capability is not required. In ad-
dition the option to abort serial data transfers is no longer
available. Hardwire CS to GND for 2-wire operation. For
the LTC2460, tie SDI LOW for 60Hz output rate and HIGH
for 30Hz output rate, for the LTC2462 tie SDI low.
Figure 13 shows a 2-wire operation sequence which uses
an idle-high (CPOL = 1) serial clock signal. The conversion
status can be monitored at the SDO output. Following a
conversion cycle, the ADC enters the data output state
and the SDO output transitions from HIGH to LOW. Sub-
sequently 16 clock pulses are applied to the SCK input in
order to serially shift the 16 bit result. Finally, the 17th
clock pulse is applied to the SCK input in order to trigger
a new conversion cycle.
Figure 14 shows a 2-wire operation sequence which uses
an idle-low (CPOL = 0) serial clock signal. The conversion
status cannot be monitored at the SDO output. Following
a conversion cycle, the LTC2460/LTC2462 enters the DATA
OUTPUT state. At this moment the SDO pin outputs the
sign (D15) of the conversion result. The user must use
external timing in order to determine the end of conversion
and result availability. Subsequently 16 clock pulses are
applied to SCK in order to serially shift the 16-bit result.
The 16th clock falling edge triggers a new conversion
cycle. For the LTC2460 tie SDI LOW for 60Hz output rate
and HIGH for 30Hz output rate.
Figure 13. 2-Wire, Idle-High (CPOL = 1) Serial Clock, Operation Example
Figure 14. 2-Wire, Idle-Low (CPOL = 0) Serial Clock Operation Example
24602 F13
D
15
D
14
D
13
D
12
D
2
D
1
D
0
SD0
clk
1
clk
2
clk
3
clk
4
clk
15
clk
16
clk
17
SCK
CONVERT
SDI = 0 OR 1
CONVERTDATA OUTPUT
CS = LOW
24602 F14
D
15
D
14
D
13
D
12
D
2
D
1
D
0
SD0
CS = LOW
clk
1
clk
2
clk
3
clk
14
clk
4
clk
15
clk
16
SCK
CONVERT CONVERTDATA OUTPUT
SDI = 0 OR 1