Datasheet

LTC2460/LTC2462
11
24602fa
applicaTions inForMaTion
used during the CONVERT and SLEEP states to assess the
conversion status and during the DATA OUTPUT state to
read the conversion result, and to trigger a new conversion.
Serial Interface Operation Modes
The modes of operation can be summarized as follows:
1) The LTC2460/LTC2462 function with SCK idle high
(commonly known as CPOL = 1) or idle low (commonly
known as CPOL = 0).
2) After the 16th bit is read, a new conversion is started
if CS is pulled high or SCK is pulled low.
3) At any time during the Data Output state, pulling CS
high causes the part to leave the I/O state, abort the
output and begin a new conversion.
4) When SCK = HIGH, it is possible to monitor the conver-
sion status by pulling CS low and watching for SDO to
go low. This feature is available only in the idle-high
(CPOL = 1) mode.
Serial Clock Idle-High (CPOL = 1) Examples
In Figure 6, following a conversion cycle the LTC2460/
LTC2462 automatically enter the NAP mode with the ADC
powered down. The ADC’s reference will power down if the
SLP bit was set high prior to the just completed conversion
and CS is HIGH. Once CS goes low, the device powers up.
The user can monitor the conversion status at convenient
intervals using CS and SDO.
Pulling CS LOW while SCK is HIGH tests whether
or not the chip is in the CONVERT state. While in
the CONVERT state, SDO is HIGH while CS is LOW.
Once the conversion is complete, SDO is LOW
Figure 5. Conversion Status Monitoring Mode
NAP
t
1
t
2
SDO
SCK = HIGH
SDI = LOW
CONVERT
24602 F05
CS
Figure 6. Idle-High (CPOL = 1) Serial Clock Operation Example.
The Rising Edge of CS Starts a New Conversion
D
15
clk
1
clk
2
clk
3
clk
4
clk
15
clk
16
D
14
D
13
D
12
D
2
D
1
D
0
SD0
SCK
CONVERT CONVERTNAP DATA OUTPUT
24602 F06
CS
SDI
EN2 SPD SLP
EN1