Datasheet
LTC2461/LTC2463
9
24613fa
V
REF
and below GND, if the differential input is within
±V
REF
. As an example (Figure 3), if the user desires to
measure a signal slightly below ground, the user could
set V
IN
–
= GND. If V
IN
+
= GND, the output code would be
approximately 32768. If V
IN
+
= GND – 8LSB = –0.305mV,
the output code would be approximately 32760.
For ap-
plications that require an input range greater than ±1.25V,
please refer to the LTC2453.
the data line is free, it is HIGH. Data on the I
2
C bus can be
transferred at rates up to 100kbits/s in the Standard-Mode
and up to 400kbits/s in the Fast-Mode.
Upon entering the DATA INPUT/OUTPUT state,
SDA
outputs
the sign (D15) of the conversion result. During this state,
the ADC shifts the conversion result serially through the
SDA
output pin under the control of the SCL input pin.
There is no latency in generating this data and the result
corresponds to the last completed conversion. A new bit
of data appears at the
SDA
pin following each falling edge
detected at the SCL input pin and appears from MSB to LSB.
The user can reliably latch this data on every rising edge
of the external serial clock signal driving the SCL pin.
Each device on the I
2
C bus is recognized by a unique
address stored in that device and can operate either as
a transmitter or receiver, depending on the function of
the device. In addition to transmitters and receivers,
devices can also be considered as masters or slaves when
performing data transfers. A master is the device which
initiates a data transfer on the bus and generates the
clock signals to permit that transfer. Devices addressed
by the master are considered a slave. The address of the
LTC2461/LTC2463 is 0010100 (if A0 is tied to GND) or
1010100 (if A0 is tied to V
CC
).
The LTC2461/LTC2463 can only be addressed as a slave.
It can only transmit the last conversion result. The serial
clock line, SCL, is always an input to the LTC2461/LTC2463
and the serial data line SDA is bidirectional. Figure 4 shows
the definition of the I
2
C timing.
APPLICATIONS INFORMATION
Figure 4. Definition of Timing for Fast/Standard Mode Devices on the I
2
C Bus
SDA
SCL
S Sr P S
t
HD(STA)
t
HD(DAT)
t
SU(STA)
t
SU(STO)
t
SU(DAT)
t
LOW
t
HD(SDA)
t
SP
t
BUF
t
r
t
f
t
r
t
f
t
HIGH
24613 F04
Figure 3. Output Code vs V
IN
+
with V
IN
–
= 0 (LTC2463)
V
IN
+
/V
REF
+
–0.001
OUTPUT CODE
4
12
20
0.001
24613 F03
–4
–12
0
8
16
–8
–16
–20
–0.005
0
0.005
0.0015
SIGNALS
BELOW
GND
I
2
C INTERFACE
The LTC2461/LTC2463 communicate through an I
2
C in-
terface. The I
2
C interface is a 2-wire open-drain interface
supporting multiple devices and masters on a single bus.
The connected devices can only pull the data line (SDA)
LOW and can never drive it HIGH. SDA must be externally
connected to the supply through a pull-up resistor. When