Datasheet

LTC2461/LTC2463
7
24613fa
APPLICATIONS INFORMATION
CONVERTER OPERATION
Converter Operation Cycle
The LTC2461/LTC2463 are low power, delta sigma, ana-
log to digital converters with a simple I
2
C interface (see
Figure 1). The LTC2463 has a fully differential input while
the LTC2461 is single-ended. Both are pin and software
compatible. Their operation is composed of three distinct
states: CONVERT, SLEEP/NAP, and DATA INPUT/OUTPUT
(see Figure 2). The operation begins with the CONVERT
state. Once the conversion is finished, the converter auto-
matically powers down (NAP) or, under user control, both
the converter and reference are powered down (SLEEP).
The conversion result is held in a static register while the
device is in this state. The cycle concludes with the DATA
INPUT/OUTPUT state. Once all 16-bits are read the device
begins a new conversion.
The CONVERT state duration is determined by the LTC2461/
LTC2463 conversion time (nominally 16.6 milliseconds).
Once started, this operation can not be aborted except by a
low power supply condition (V
CC
< 2.1V) which generates
an internal power-on reset signal.
After the completion of a conversion, the LTC2461/LTC2463
enters the SLEEP/NAP state and remains there until a valid
Figure 2. LTC2461/LTC2463 State Transition Diagram
read/write is acknowledged. Following this condition, the
ADC transitions into the DATA INPUT/OUTPUT state.
While in the SLEEP/NAP state, the LTC2461/LTC2463’s
converters are powered down. This reduces the supply
DATA INPUT/OUTPUT
SLEEP/NAP
CONVERT
POWER-ON RESET
YES
24613 F02
STOP
OR
READ 16 BITS
READ/WRITE
ACKNOWLEDGE
NO YES
NO
BLOCK DIAGRAM
Figure 1. Functional Block Diagram
∆Σ A/D
CONVERTER
DECIMATING
SINC FILTER
SDA
REFOUT COMP
REF
–
IN
+
(IN)
IN
–
(GND)
SCL
A0
24613 BD
–
∆Σ A/D
CONVERTER
INTERNAL
REFERENCE
( ) PARENTHESIS INDICATE LTC2461
I
2
C
INTERFACE
INTERNAL
OSCILLATOR
1
V
CC
122
3
5
6
8
GND
4, 7, 11, 13 (DD PACKAGE)
9
10