Datasheet

LTC2461/LTC2463
14
24613fa
APPLICATIONS INFORMATION
REFOUT and COMP
The on-chip 1.25V precision reference is internally tied
to the LTC2461/LTC2463 converter’s reference input and
its output to the REFOUT pin. A 0.1μF capacitor should
be placed on the REFOUT pin. It is possible to reduce
this capacitor, but the transition noise increases. A 0.1μF
capacitor should also be placed on the COMP pin. This
pin is tied to an internal point in the reference and is used
for stability. In order for the reference to remain stable the
capacitor placed on the COMP pin must be greater than or
equal to the capacitor tied to the REFOUT pin. The REFOUT
pin should not be overridden by an external voltage. If
a reference voltage greater than 1.25V is required, the
LTC2451/LTC2453 should be used.
The internal reference has a corresponding start up
time depending on the size of the capacitors tied to the
REFOUT and COMP pins. This start up time is typically
12ms when 0.1μF capacitors are used. At initial power up,
the first conversion result can be aborted or ignored. At
the completion of this first conversion, the reference has
settled and all subsequent conversions are valid.
If the reference is put to sleep (program SLP = 1) the refer-
ence is powered down after the next conversion. This last
conversion result is valid. On a valid address acknowledge,
the reference is powered back up. In order to ensure the
reference output has settled before the next conversion,
the power up time can be extended by delaying the data
read 12ms. Once all 16 bits are read from the device, the
next conversion automatically begins. In the default opera-
tion, the reference remains powered up at the conclusion
of the conversion cycle.
Driving V
IN
+
and V
IN
–
The input drive requirements can best be analyzed using
the equivalent circuit of Figure 9. The input signal V
SIG
is
connected to the ADC input pins (IN
+
and IN
–
) through an
equivalent source resistance R
S
. This resistor includes both
the actual generator source resistance and any additional
optional resistors connected to the input pins. Optional
input capacitors C
IN
are also connected to the ADC input
pins. This capacitor is placed in parallel with the input
parasitic capacitance C
PAR
. This parasitic capacitance
Figure 9. LTC2461/LTC2463 Input Drive Equivalent Circuit
I
LEAK
I
LEAK
R
SW
15k
(TYP)
I
CONV
C
IN
IN
+
(LTC2463)
IN
(LTC2461)
V
CC
V
SIG
+
V
SIG
–
R
S
C
EQ
0.35pF
(TYP)
C
PAR
+
–
24613 F09
I
LEAK
I
LEAK
R
SW
15k
(TYP)
I
CONV
C
IN
IN
–
(LTC2463)
V
CC
R
S
C
EQ
0.35pF
(TYP)
C
PAR
+
–
includes elements from the printed circuit board (PCB)
and the associated input pin of the ADC. Depending on the
PCB layout, C
PAR
has typical values between 2pF and 15pF.
In addition, the equivalent circuit of Figure 9 includes the
converter equivalent internal resistor R
SW
and sampling
capacitor C
EQ
.
There are some immediate trade-offs in R
S
and C
IN
without
needing a full circuit analysis. Increasing R
S
and C
IN
can
give the following benefits:
1) Due to the LTC2461/LTC2463’s input sampling algo-
rithm, the input current drawn by IN
+
, IN
–
or IN over
a conversion cycle is typically 50nA. A high R
S
• C
IN
attenuates the high frequency components of the input
current, and R
S
values up to 1k result in <1LSB error.
2) The bandwidth from V
SIG
is reduced at the input pins
(IN
+
, IN
–
or IN). This bandwidth reduction isolates the
ADC from high frequency signals, and as such provides
simple antialiasing and input noise reduction.
3) Switching transients generated by the ADC are attenu-
ated before they go back to the signal source.
4) A large C
IN
gives a better AC ground at the input pins,
helping reduce reflections back to the signal source.
5) Increasing R
S
protects the ADC by limiting the current
during an outside-the-rails fault condition.
There is a limit to how large R
S
• C
IN
should be for a given
application. Increasing R
S
beyond a given point increases
the voltage drop across R
S
due to the input current,