Datasheet

LTC2461/LTC2463
13
24613fa
APPLICATIONS INFORMATION
conversion cycle. The master issues a START, followed
by the LTC2461/LTC2463 global address 1110111, and a
write request. The LTC2461/LTC2463 will be selected and
acknowledge the request. If desired, the master then sends
the write byte to program the 30Hz or 60Hz mode. After
the optional write byte, the master ends the write operation
with a STOP. This will update the configuration registers
(if a write byte was sent) and initiate a new conversion on
the LTC2461/LTC2463, as shown in Figure7c. In order to
synchronize the start of the conversion without affecting
the configuration registers, the write operation can be
aborted with a STOP. This initiates a new conversion on
the LTC2461/LTC2463 without changing the configura-
tion registers.
PRESERVING THE CONVERTER ACCURACY
The LTC2461/LTC2463 are designed to minimize the conver-
sion result’s sensitivity to device decoupling, PCB layout,
antialiasing circuits, line and frequency perturbations. Nev-
ertheless, in order to preserve the high accuracy capability
of this part, some simple precautions are desirable.
Digital Signal Levels
Due to the nature of CMOS logic, it is advisable to keep
input digital signals near GND or V
CC
. Voltages in the range
of 0.5V to V
CC
– 0.5V may result in additional current
leakage from the part. Undershoot and overshoot should
also be minimized, particularly while the chip is convert-
ing. Excessive noise on the digital lines could degrade the
ADC performance.
Driving V
CC
and GND
In relation to the V
CC
and GND pins, the LTC2461/LTC2463
combines internal high frequency decoupling with damping
elements, which reduce the ADC performance sensitivity
to PCB layout and external components. Nevertheless,
the very high accuracy of this converter is best pre-
served by careful low and high frequency power supply
decoupling.
A 0.1µF, high quality, ceramic capacitor in parallel with
a 10µF low ESR ceramic capacitor should be connected
between the V
CC
and GND pins, as close as possible to
the package. The 0.1µF capacitor should be placed closest
to the ADC package. It is also desirable to avoid any via
in the circuit path, starting from the converter V
CC
pin,
passing through these two decoupling capacitors, and
returning to the converter GND pin. The area encompassed
by this circuit path, as well as the path length, should be
minimized.
As shown in Figure 8, REF
–
is used as the negative refer-
ence voltage input to the ADC. This pin can be tied directly
to ground or Kelvined to sensor ground. In the case where
REF
–
is used as a sense input, it should be bypassed to
ground with a 0.1μF ceramic capacitor in parallel with a
10μF low ESR ceramic capacitor.
Very low impedance ground and power planes, and star
connections at both V
CC
and GND pins, are preferable.
The V
CC
pin should have two distinct connections: the
first to the decoupling capacitors described above, and
the second to the ground return for the power supply
voltage source.
Figure 8. LTC2461/LTC2463 Analog Input/Reference
Equivalent Circuit
R
SW
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V
CC
V
CC
V
CC
V
CC
C
EQ
0.35pF
(TYP)
IN
+
IN
–
REF
–
REFOUT
INTERNAL
REFERENCE
24613 F08
R
SW
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(TYP)
I
LEAK
I
LEAK
R
SW
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R
SW
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(TYP)
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