Datasheet
LTC2461/LTC2463
11
24613fa
APPLICATIONS INFORMATION
Data Input Format
After a START condition, the master sends a 7-bit ad-
dress followed by a read/write request (R/W) bit. The
R/W bit is 0 for a write. The data input word is 4 bits long
and consists of two enable bits (EN1 and EN2) and two
programming bits (SPD and SLP), see Figure 5b. EN1 is
applied to the first rising edge of SCL after a valid write
address is acknowledged. Programming is enabled by
setting EN1 = 1 and EN2 = 0.
The speed bit (SPD) is only used by the LTC2461. In the
default mode, SPD = 0, the output rate is 60Hz and con-
tinuous background offset calibration is not performed. By
changing the SPD bit to 1, background offset calibration
is performed and the output rate is reduced to 30Hz. The
LTC2463 data output rate is always 60Hz and background
offset calibration is performed (SPD = don’t care).
The sleep bit (SLP) is used to power down the on chip
reference. In the default mode, the reference remains
powered up even when the ADC is powered down. If the
SLP bit is set HIGH, the reference will power down after
the next conversion is complete. It will remain powered
down until a valid address is acknowledged. The reference
startup time is approximately 12ms. In order to ensure a
stable reference for the following conversions, either the
data input/output time should be delayed 12ms after an
address acknowledge or the first conversion following a
reference start up should be discarded.
Figure 5b. Timing Diagram for Writing to the LTC2461/LTC2463
SDA
SCL
EN1 EN2 SPD SLP
W
SLEEP
START BY
MASTER
DATA INPUT
7 8 9
1 2 3 4 5 6 7 8 9
1 2 …
7-BIT ADDRESS
ACK BY
LTC2461/LTC2463
ACK BY
LTC2461/LTC2463
24613 F03
Table 1. LTC2461/LTC2463 Output Data Format
SINGLE ENDED INPUT V
IN
(LTC2461)
DIFFERENTIAL INPUT VOLTAGE
V
IN
+
– V
IN
–
(LTC2463)
D15
(MSB)
D14 D13 D12...D2 D1 D0
(LSB)
CORRESPONDING
DECIMAL VALUE
≥V
REF
≥V
REF
1 1 1 1 1 1 65535
V
REF
– 1LSB V
REF
– 1LSB 1 1 1 1 1 0 65534
0.75 • V
REF
0.5 • V
REF
1 1 0 0 0 0 49152
0.75 • V
REF
– 1LSB 0.5 • V
REF
– 1LSB 1 0 1 1 1 1 49151
0.5 • V
REF
0 1 0 0 0 0 0 32768
0.5 • V
REF
– 1LSB –1LSB 0 1 1 1 1 1 32767
0.25 • V
REF
–0.5 • V
REF
0 1 0 0 0 0 16384
0.25 • V
REF
– 1LSB –0.5 • V
REF
– 1LSB 0 0 1 1 1 1 16383
0 ≤ –V
REF
0 0 0 0 0 0 0