Datasheet

LTC2460/LTC2462
12
24602fa
while CS is LOW. These tests are not required op-
erational steps but may be useful for some applications.
When the data is available, the user applies 16 clock cycles
to transfer the result. The CS rising edge is then used to
initiate a new conversion.
The operation example of Figure 7 is identical to that of
Figure 6, except the new conversion cycle is triggered by
the falling edge of the serial clock (SCK).
Serial Clock Idle-Low (CPOL = 0) Examples
In Figure 8, following a conversion cycle the LTC2460/
LTC2462 automatically enters the NAP state. The device
reference will power down if the SLP bit was set high
prior to the just completed conversion and CS is HIGH.
Once CS goes low, the reference powers up. The user
determines data availability (and the end of conversion)
based upon external timing. The user then pulls CS low
(CS = ↓) and uses 16 clock cycles to transfer the result.
Following the 16th rising edge of the clock, CS is pulled high
(CS = ↑), which triggers a new conversion.
The timing diagram in Figure 9 is identical to that of Figure 8,
except in this case a new conversion is triggered by SCK.
The 16th SCK falling edge triggers a new conversion cycle
and the CS signal is subsequently pulled high.
Examples of Aborting Cycle using CS
For some applications, the user may wish to abort the I/O
cycle and begin a new conversion. If the LTC2460/LTC2462
are in the data output state, a CS rising edge clears the
remaining data bits from the output register, aborts the out-
put cycle and triggers a new conversion. Figure 10 shows
an example of aborting an I/O with idle-high (CPOL = 1)
and Figure 11 shows an example of aborting an I/O with
idle-low (CPOL = 0).
A new conversion cycle can be triggered using the CS
signal without having to generate any serial clock pulses
as shown in Figure 12. If SCK is maintained at a low logic
level, after the end of a conversion cycle, a new conver-
sion operation can be triggered by pulling CS low and
then high. When CS is pulled low (CS = LOW), SDO will
applicaTions inForMaTion
Figure 8. Idle-Low (CPOL = 0) Clock. CS Triggers a New Conversion
D
15
D
14
D
13
D
12
D
2
D
1
D
0
clk
1
clk
2
clk
3
clk
4
clk
14
clk
15
clk
16
SCK
SD0
CONVERT CONVERTNAP DATA OUTPUT
24602 F08
CS
SDI
EN2 SPD SLP
EN1
Figure 7. Idle-High (CPOL = 1) Clock Operation Example.
A 17th Clock Pulse is Used to Trigger a New Conversion Cycle
D
15
D
14
D
13
D
12
D
2
D
1
D
0
SD0
clk
1
clk
2
clk
3
clk
4
clk
15
clk
16
clk
17
SCK
CONVERT CONVERTNAP DATA OUTPUT
24602 F07
CS
SDI
EN2 SPD SLP
EN1