Datasheet
LTC2757
9
2757f
PIN FUNCTIONS
V
OSADJ
(Pin 39): DAC Offset Adjust Pin. This voltage-control
pin can be used to null unipolar offset or bipolar zero error.
The offset change expressed in LSB is the same for any
output range. See
System Offset and Gain Adjustments
in
the Operation section. Tie to ground if not used.
I
OUT1
(Pin 40): DAC current output; normally tied to the
negative input (summing junction) of the I/V converter
amplifi er.
R
FB
(Pins 41, 42): DAC Feedback Resistor. Normally tied
to the output of the I/V converter amplifi er. The DAC output
current from I
OUT1
fl ows through the feedback resistor to
the R
FB
pins. These pins are internally shorted together.
R
OFS
(Pins 43, 44): Bipolar Offset Network. These pins
provide the translation of the output voltage range for
bipolar spans. Accepts up to ±15V; normally tied to the
positive reference voltage. These pins are internally shorted
together.
REF (Pins 45, 46): Feedback Resistor for the Reference
Inverting Amplifi er, and Reference Input for the DAC.
Normally tied to the output of the reference inverting
amplifi er. Typically –5V; accepts up to ±15V. These pins
are internally shorted together.
R
COM
(Pin 47): Center Tap Point of R
IN
and REF. Normally
tied to the negative input of the external reference invert-
ing amplifi er.
GE
ADJ
(Pin 48): Gain Adjust Pin. This voltage-control
pin can be used to null gain error or to compensate for
reference errors. The gain error change expressed in LSB
is the same for any output range. See
System Offset and
Gain Adjustments
in the Operation section. Tie to ground
if not used.
36
35
34
33
20
21
18-BIT DAC WITH SPAN SELECT
DAC
REGISTER
INPUT
REGISTER
R
COM
R
IN
1, 2
R2
20k
R1
20k
R
OFS
43, 44
REF
45, 46
R
FB
41, 42
I
OUT1
V
OSADJ
2.56M
I
OUT2F
I
OUT2S
WR
UPD
READ
D/S
CLR
M-SPAN
2757 BD
CONTROL
LOGIC
3
3
3
I/O
PORT
DAC
REGISTER
INPUT
REGISTER
18
18
18
I/O
PORT
40
39
47
GE
ADJ
48
6
5
3, 37, 38
SPAN I/O
S2-S0
8-16, 23-31
DATA I/O
D17-D0
BLOCK DIAGRAM