Datasheet
LTC2757
5
2757f
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
CLR Timing
t
25
CLR Pulse Width Low
l
20 ns
V
DD
= 2.7V to 3.3V
Write and Update Timing
t
1
I/O Valid to WR Rising Edge Set-Up
l
18 ns
t
2
I/O Valid to WR Rising Edge Hold
l
18 ns
t
3
WR Pulse Width
l
30 ns
t
4
UPD Pulse Width
l
30 ns
t
5
UPD Falling Edge to WR Falling Edge No Data Shoot-Through
l
0ns
t
6
WR Rising Edge to UPD Rising Edge (Note 12)
l
0ns
t
7
D/S Valid to WR Falling Edge Set-Up Time
l
18 ns
t
8
WR Rising Edge to D/S Valid Hold Time
l
18 ns
Readback Timing
t
13
WR Rising Edge to Read Rising Edge
l
18 ns
t
14
Read Falling Edge to WR Falling Edge (Note 12)
l
40 ns
t
15
Read Rising Edge to I/O Propagation Delay C
L
= 10pF
l
48 ns
t
17
UPD Valid to I/O Propagation Delay C
L
= 10pF
l
48 ns
t
18
D/S Valid to Read Rising Edge (Note 12)
l
18 ns
t
19
Read Rising Edge to UPD Rising Edge No Update
l
9ns
t
20
UPD Falling Edge to Read Falling Edge No Update
l
9ns
t
22
READ Falling Edge to UPD Rising Edge (Note 12)
l
18 ns
t
23
I/O Bus Hi-Z to Read Rising Edge (Note 12)
l
0ns
t
24
Read Falling Edge to I/O Bus Active (Note 12)
l
40 ns
CLR Timing
t
25
CLR Pulse Width Low
l
30 ns
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: Continuous operation above the specifi ed maximum operating
junction temperature may impair device reliability.
Note 3: Temperature Coeffi cient is calculated by dividing the maximum
change in the parameter by the specifi ed temperature range.
Note 4: R1 is measured from R
IN
to R
COM
; R2 is measured from REF to
R
COM
.
Note 5: Parallel combination of the resistances from REF to I
OUT1
and from
REF to I
OUT2
. DAC input resistance is independent of code.
Note 6: Because of the proprietary SoftSpan switching architecture, the
measured resistance looking into each of the specifi ed pins is constant for
all output ranges if the I
OUT1
and I
OUT2
pins are held at ground.
TIMING CHARACTERISTICS
V
DD
= 5V, V(R
IN
) = 5V unless otherwise specifi ed. The l denotes specifi cations that
apply over the full operating temperature range, otherwise specifi cations are at T
A
= 25°C.
Note 7: Using LT1468 with C
FEEDBACK
= 27pF. A ±0.0004% settling time
of 1.8s can be achieved by optimizing the time constant on an individual
basis. See Application Note 120,
1ppm Settling Time Measurement for a
Monolithic 18-Bit DAC
.
Note 8: Measured at the major carry transition, 0V to 5V range. Output
amplifi er: LT1468; C
FB
= 50pF.
Note 9: Zero-code to full-code transition; REF = 0V. Falling transition is
similar or better.
Note 10: REF = 6V
RMS
at 1kHz. 0V to 5V range. DAC code = FS. Output
amplifi er = LT1468.
Note 11: Calculation from V
n
= √4kTRB, where k = 1.38E-23 J/°K
(Boltzmann constant), R = resistance (Ω), T = temperature (°K), and B =
bandwidth (Hz).
Note 12: Guaranteed by design. Not production tested.