Datasheet

LTM4618
14
4618fa
APPLICATIONS INFORMATION
board, and is really the sum of the θ
JCbottom
and the
thermal resistance of the bottom of the part through
the solder joints and through a portion of the board.
The board temperature is measured at specifi ed dis-
tance from the package, using a two sided, two layer
board. This board is described in JESD 51-9.
A graphical representation of the forementioned thermal
resistances is given in Figure 6; blue resistances are
contained within the µModule regulator, whereas green
resistances are external to the µModule regulator.
As a practical matter, it should be clear to the reader that
no individual or sub-group of the four thermal resistance
parameters defi ned by JESD 51-12 or provided in the
Pin Confi guration section replicates or conveys normal
operating conditions of a µModule regulator. For example,
in actual board-mounted applications, never does 100%
of the device’s total power loss (heat) thermally conduct
exclusively through the top or exclusively through bot-
tom of the µModule regulator—as the standard defi nes
for θ
JCtop
and θ
JCbottom
, respectively. In practice, power
loss is thermally dissipated in both directions away from
the package—granted, in the absence of a heat sink and
airfl ow, a majority of the heat fl ow is into the board.
Within a SIP (System-In-Package) module, be aware there
are multiple power devices and components dissipating
power, with a consequence that the thermal resistances
relative to different junctions of components or die are not
exactly linear with respect to total package power loss. To
reconcile this complication without sacrifi cing modeling
simplicity—but also, not ignoring practical realities—an
approach has been taken using FEA software modeling
along with laboratory testing in a controlled-environment
chamber to reasonably defi ne and correlate the thermal
resistance values supplied in this data sheet: (1) Initially,
FEA software is used to accurately build the mechanical
geometry of the µModule regulator and the specifi ed PCB
with all of the correct material coeffi cients along with
accurate power loss source defi nitions; (2) this model
simulates a software-defi ned JEDEC environment consis-
tent with JSED51-9 to predict power loss heat fl ow and
temperature readings at different interfaces that enable
the calculation of the JEDEC-defi ned thermal resistance
values; (3) the model and FEA software is used to evalu-
ate the µModule regulator with heat sinks and airfl ow; (4)
having solved for and analyzed these thermal resistance
values and simulated various operating conditions in the
software model, a thorough laboratory evaluation replicates
the simulated conditions with thermocouples within a
controlled-environment chamber while operating the device
at the same power loss as that which was simulated. An
outcome of this process and due-diligence yields a set
of derating curves provided in other sections of this data
sheet. After these laboratory tests have been performed
and correlated to the µModule package model, then the
θ
JB
and θ
BA
are summed together to correlate quite well
with the µModule package model with no air fl ow or heat
sinking in a properly defi ne chamber. This θ
JB
+ θ
BA
value
is shown in the Pin Confi guration section and should ac-
curately equal the θ
JA
value because approximately 100%
of power loss fl ows from the junction through the board
into ambient with no airfl ow or top mounted heat sink.
4618 F06
µMODULE DEVICE
JUNCTION-TO-CASE (TOP)
RESISTANCE
JUNCTION-TO-BOARD RESISTANCE
JUNCTION-TO-AMBIENT RESISTANCE (JESD 51-9 DEFINED BOARD)
CASE (TOP)-TO-AMBIENT
RESISTANCE
BOARD-TO-AMBIENT
RESISTANCE
JUNCTION-TO-CASE
(BOTTOM) RESISTANCE
JUNCTION A
t
CASE (BOTTOM)-TO-BOARD
RESISTANCE
Figure 6. Graphical Representation of JESD51-12 Thermal Coeffi cients