Datasheet

LTC2301/LTC2305
4
23015fb
DYNAMIC ACCURACY
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
SINAD Signal-to-(Noise + Distortion) Ratio f
IN
= 1kHz
l
71 73.4 dB
SNR Signal-to-Noise Ratio f
IN
= 1kHz
l
71 73.5 dB
THD Total Harmonic Distortion f
IN
= 1kHz
l
–91 –77 dB
SFDR Spurious Free Dynamic Range f
IN
= 1kHz, First 5 Harmonics
l
79 92 dB
Channel-to-Channel Isolation f
IN
= 1kHz –109 dB
Full Linear Bandwidth f
IN
= 1kHz 700 kHz
–3dB Input Linear Bandwidth (Note 10) 25 MHz
Aperture Delay 13 ns
Transient Response Full-Scale Step 240 ns
The l denotes the specifi cations which apply over the full operating temperature range,
otherwise specifi cations are at T
A
= 25°C and A
IN
= –1dBFS. (Notes 4,9)
INTERNAL REFERENCE CHARACTERISTICS
The l denotes the specifi cations which apply over the full operating temperature range, otherwise specifi cations are at T
A
= 25°C. (Notes 4)
PARAMETER CONDITIONS MIN TYP MAX UNITS
V
REF
Output Voltage I
OUT
= 0
l
2.46 2.50 2.54 V
V
REF
Output Tempco I
OUT
= 0 ±25 ppm/°C
V
REF
Output Impedance –0.1mA ≤ I
OUT
≤ 0.1mA 8 kΩ
V
REFCOMP
Output Voltage I
OUT
= 0 4.096 V
V
REF
Line Regulation V
DD
= 4.75V to 5.25V 0.8 mV/V
I
2
C INPUTS AND DIGITAL OUTPUTS
The l denotes the specifi cations which apply over the full operating temperature range, otherwise specifi cations are at T
A
= 25°C. (Notes 4)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
V
IH
High Level Input Voltage
l
2.85 V
V
IL
Low Level Input Voltage
l
1.5 V
V
IHA
High Level Input Voltage for Address Pins A1, A0
l
4.75 V
V
ILA
Low Level Input Voltage for Address Pins A1, A0
l
0.25 V
R
INH
Resistance from A1, A0 to V
DD
to Set Chip
Address Bit to 1
l
10 k
R
INL
Resistance from A1, A0 to GND to Set Chip
Address Bit to 0
l
10 k
R
INF
Resistance from A1, A0 to GND or V
DD
to Set
Chip Address Bit to Float
l
2M
I
I
Digital Input Current V
IN
= V
DD
l
–10 10 A
V
HYS
Hysteresis of Schmitt Trigger Inputs (Note 8)
l
0.25 V
V
OL
Low Level Output Voltage (SDA) I = 3mA
l
0.4 V
t
OF
Output Fall Time V
IN(MIN)
to V
IL(MAX)
Bus Load C
B
10pF to 400pF (Note 11)
l
20 + 0.1C
B
250 ns
t
SP
Input Spike Suppression
l
50 ns
C
CAX
External Capacitance Load on Chip Address Pins
(A1, A0) for Valid Float
l
10 pF