Datasheet

LTC2301/LTC2305
12
23015fb
APPLICATIONS INFORMATION
Overview
The LTC2301/LTC2305 are low noise, 1-/2-channel, 12-bit
successive approximation register (SAR) A/D converters
with an I
2
C compatible serial interface. The LTC2301/
LTC2305 both include a precision internal reference. The
LTC2305 includes a 2-channel analog input multiplexer
(MUX) while the LTC2301 includes an input MUX that allows
the polarity of the differential input to be selected. These
ADCs can operate in either unipolar or bipolar mode. Uni-
polar mode should be used for single-ended operation with
the LTC2305, since single-ended input signals are always
referenced to GND. A sleep mode option is also provided
to further reduce power during inactive periods.
The LTC2301/LTC2305 communicate through a 2-wire
I
2
C compatible serial interface. Conversions are initiated
by signaling a STOP condition after the part has been
successfully addressed for a read/write operation. The
device will not acknowledge an external request until the
conversion is fi nished. After a conversion is fi nished, the
device is ready to accept a read/write request. Once the
LTC2301/LTC2305 is addressed for a read operation, the
device begins outputting the conversion result under the
control of the serial clock (SCL). There is no latency in
the conversion result. There are 12 bits of output data fol-
lowed by four trailing zeros. Data is updated on the falling
edges of SCL, allowing the user to reliably latch data on
the rising edge of SCL. A write operation may follow the
read operation by using a repeat START or a STOP condi-
tion may be given to start a new conversion. By selecting
a write operation, these ADCs can be programmed by a
6-bit D
IN
word. The D
IN
word confi gures the MUX and
programs various modes of operation.
During a conversion, the internal 12-bit capacitive charge-
redistribution DAC output is sequenced through a succes-
sive approximation algorithm by the SAR starting from
the most signifi cant bit (MSB) to the least signifi cant bit
(LSB). The sampled input is successively compared with
binary weighted charges supplied by the capacitive DAC
using a differential comparator. At the end of a conver-
sion, the DAC output balances the analog input. The SAR
contents (a 12-bit data word) that represent the sampled
analog input are loaded into 12 output latches that allow
the data to be shifted out via the I
2
C interface.
Programming the LTC2301 and LTC2305
The software compatible LTC2301/LTC2305/LTC2309 fam-
ily features a 6-bit D
IN
word to program various modes of
operation. Don’t care bits (X) are ignored. The SDA data
bits are loaded on the rising edge of SCL during a write
operation, with the S/D bit loaded on the fi rst rising edge
and the SLP bit on the sixth rising edge (see Figure 7b
in the I
2
C Interface section). The input data word for the
LTC2305 is defi ned as follows:
S/D O/S X X UNI SLP
S/D = SINGLE-ENDED/DIFFERENTIAL BIT
O/S = ODD/SIGN BIT
UNI = UNIPOLAR/BIPOLAR BIT
SLP = SLEEP MODE BIT
For the LTC2301, the input word is defi ned as:
X O/S X X UNI SLP
Analog Input Multiplexer
The analog input MUX is programmed by the S/D and
O/S bits of the D
IN
word for the LTC2305 and the O/S
bit of the D
IN
word for the LTC2301. Table 1 and Table 2
list the MUX confi gurations for all combinations of the
confi guration bits. Figure 1a shows several possible MUX
confi gurations and Figure 1b shows how the MUX can be
reconfi gured from one conversion to the next.
Table 1. Channel Confi guration for the LTC2305
S/D O/S CH0 CH1
00+–
01–+
10+
11 +