Datasheet

LTC2301/LTC2305
9
23015fb
PIN FUNCTIONS
GND (Pins 1, 4, 9): Ground. All GND pins must be con-
nected to a solid ground plane.
SDA (Pin 2): Bidirectional Serial Data Line of the I
2
C In-
terface. In transmitter mode (read), the conversion result
is output at the SDA pin, while in receiver mode (write),
the D
IN
word is input at the SDA pin to confi gure the ADC.
The pin is high impedance during the data input mode and
is an open drain output (requires an appropriate pull-up
device to V
DD
) during the data output mode.
SCL (Pin 3): Serial Clock Pin of the I
2
C Interface. The
LTC2301 can only act as a slave and the SCL pin only ac-
cepts an external serial clock. Data is shifted into the SDA
pin on the rising edges of the SCL clock and output through
the SDA pin on the falling edges of the SCL clock.
IN
+
, IN
–
(Pins 5, 6): Positive (IN
+
) and negative (IN
–
)
differential analog inputs.
V
REF
(Pin 7): 2.5V Reference Output. Bypass to GND with
a minimum 2.2µF ceramic capacitor. The internal refer-
ence may be overdriven by an external 2.5V reference at
this pin.
REFCOMP (Pin 8): Reference Buffer Output. Bypass to
GND with 10µF and 0.1µF ceramic capacitors in parallel.
Nominal output voltage is 4.096V. The internal reference
buffer driving this pin is disabled by grounding V
REF
, al-
lowing REFCOMP to be overdriven by an external source
(see Figure 5c).
V
DD
(Pin 10): 5V Analog Supply. The range of V
DD
is 4.75V
to 5.25V. Bypass V
DD
to GND with 10µF and 0.1µF ceramic
capacitors in parallel.
AD1 (Pin 11): Chip Address Control Pin. This pin is con-
fi gured as a three-state (LOW, HIGH, fl oating) address
control bit for the device I
2
C address. See Table 2 for
address selection.
AD0 (Pin 12): Chip Address Control Pin. This pin is con-
fi gured as a three-state (LOW, HIGH, fl oating) address
control bit for the device I
2
C address. See Table 2 for
address selection.
GND (Pin 13 – DFN Package Only): Exposed Pad Ground.
Must be soldered directly to ground plane.
(LTC2301)