Datasheet

LTC2301/LTC2305
20
23015fb
APPLICATIONS INFORMATION
Sleep Mode
The ADCs enter sleep mode after a conversion is complete
(t
CONV
) if the SLP bit is set to a logic 1. The ADCs draw
only 7µA in sleep mode, provided that none of the digital
inputs are switching. When the LTC2301/LTC2305 are
properly addressed, the ADCs are released from sleep
mode and require 200ms (t
REFWAKE
) to wake up and charge
the respective 2.2F and 10F bypass capacitors on the
V
REF
and REFCOMP pins. A new conversion should not be
initiated before this time, as shown in Figure 11.
Acquisition
The LTC2301/LTC2305 begin acquiring the input signal at
different instances depending on whether a read or write
operation is being performed. If a read operation is being
performed, acquisition of the input signal begins on the
rising edge of the 9th clock pulse following the address
frame, as shown in Figure 12a.
If a write operation is being performed, acquisition of the
input signal begins on the falling edge of the sixth clock
cycle after the D
IN
word has been shifted in, as shown in
Figure 12b. The LTC2301/LTC2305 will acquire the signal
from the input channel that was most recently programmed
by the D
IN
word. A minimum of 240ns is required to acquire
the input signal before initiating a new conversion.
Board Layout and Bypassing
To obtain the best performance, a printed circuit board with
a solid ground plane is required. Layout for the printed
board should ensure digital and analog signal lines are
S
CONVERSION SLEEP t
REFWAKE
CONVERSION
R/W ACK7-BIT ADDRESS P
23015 F11
Figure 11. Exiting Sleep Mode and Starting a New Conversion
Figure 12a. Timing Diagram Showing Acquisition During a Read Operation
12
A6SDA
SCL
A5 A4 A3 A2 A1 A0 R/W
3456789 12
B11
ACQUISITION BEGINS
t
ACQ
23015 F12a
B10
Figure 12b. Timing Diagram Showing Acquisition During a Write Operation
12
A2 A1 A0 R/WSDA
SCL
S/D O/S X X UNI X X
34556789 6789
ACQUISITION BEGINS
t
ACQ
23015 F12b
SLP