Datasheet

LTC2301/LTC2305
18
23015fb
APPLICATIONS INFORMATION
After power-up, the ADC initiates an internal reset cycle
which sets the D
IN
word to all 0s (S/D=O/S=UNI=SLP=0).
A write operation may be performed if the default state
of the ADC’s confi guration is not desired. Otherwise, the
ADC must be properly addressed and followed by a STOP
condition to initiate a conversion.
Initiating a New Conversion
The LTC2301/LTC2305 awakens from either nap or sleep
when properly addressed for a read/write operation. A
STOP command may then be issued after performing the
read/write operation to trigger a new conversion.
Issuing a STOP command after the 8th SCL clock pulse of
the address frame and before the completion of a read/write
operation will also initiate new conversion, but the output
result may not be valid due to lack of adequate acquisition
time (see Acquisition section).
LTC2301/LTC2305 Address
The LTC2301/LTC2305 have two address pins (AD0 and
AD1) that may be tied high, low or left fl oating to enable
one of the 9 possible addresses (see Table 2).
In addition to the confi gurable addresses listed in Table 2,
the LTC2301/LTC2305 also contain a global address
(1101011) which may be used for synchronizing multiple
LTC2301/LTC2305s or other I
2
C LTC230X SAR ADCs (see
Synchronizing Multiple LTC2301/LTC2305s with Global
Address Call section).
Table 2. Address Assignment
AD1 AD0 ADDRESS
LOW LOW 0001000
LOW Float 0001001
LOW HIGH 0001010
Float HIGH 0001011
Float Float 0011000
Float LOW 0011001
HIGH LOW 0011010
HIGH Float 0011011
HIGH HIGH 0101000
Continuous Read
In applications where the same input channel is sampled
each cycle, conversions can be continuously performed
and read without a write cycle (see Figure 8). The D
IN
word
remains unchanged from the last value written into the
device. If the device has not been written to since power-
up, the D
IN
word defaults to all 0s (S/D=O/S=UNI=SLP=0).
At the end of a read operation, a STOP condition may be
given to start a new conversion. At the conclusion of the
conversion cycle, the next result may be read using the
method described above. If the conversion cycle is not
concluded and a valid address selects the device, the
LTC2301/LTC2305 generates a NACK signal indicating the
conversion cycle is in progress.
Figure 8. Consecutive Reading with the Same Confi guration
S
CONVERSION NAP DATA OUTPUT CONVERSION CONVERSIONNAP DATA
OUTPUT
R ACK READ7-BIT ADDRESS P S R ACK
23015 F08
READ7-BIT ADDRESS P