Datasheet

LTC2301/LTC2305
11
23015fb
FUNCTIONAL BLOCK DIAGRAM
23015 BD
+
–
12-BIT
SAR ADC
ANALOG
INPUT
MUX
I
2
C
PORT
INTERNAL
2.5V REF
GAIN = 1.6384x
V
REF
REFCOMP
SCL
SDA
AD1
AD0
CH0(IN
+
)
CH1(IN
–
)
PIN NAMES IN PARENTHESES
REFER TO LTC2301
V
DD
LTC2301
LTC2305
8k
GND
TIMING DIAGRAM
SDA
SCL
SSrPS
t
HD(SDA)
S = START, Sr = REPEATED START, P = STOP
t
HD(DAT)
t
SU(STA)
t
SU(STO)
t
SU(DAT)
t
LOW
t
HD(SDA)
t
SP
t
BUF
t
r
t
r
t
f
t
f
t
HIGH
23015 TD
Defi nition of Timing for Fast/Standard Mode Devices on the I
2
C Bus