Datasheet

LTC4265
15
4265fa
Figure 9. T2PSE Interface Examples
4265 F09
OPTION 1: SERIES CONFIGURATION FOR ACTIVE LOW/LOW IMPEDANCE OUTPUT
–54V
TO
PSE
R
P
TO PD LOAD
GND
LTC4265
V
IN
T2PSE
V
+
OPTION 2: SHUNT CONFIGURATION FOR ACTIVE HIGH/OPEN COLLECTOR OUTPUT
–54V
TO
PSE
R
P
TO PD LOAD
GND
LTC4265
V
IN
V
OUT
T2PSE
V
+
APPLICATIONS INFORMATION
Figure 8. Power Good Interface Examples
GND
R
S
10k
R10
100k
PWRGD
D9
MMBD4148
Q1
FMMT2222
–54V
4265 F08
TO
PSE
LTC4265
ACTIVE-LOW ENABLE
V
IN
V
OUT
V
+
PD
LOAD
GND
R
S
10k
R9
100k
PWRGD
D9
5.1V
MMBZ5231B
–54V
TO
PSE
LTC4265
ACTIVE-LOW ENABLE
V
IN
V
OUT
PD
LOAD
–54V
TO
PSE
ACTIVE-HIGH ENABLE
PD
LOAD
RUN
SHDN
GND
PWRGD
LTC4265
V
IN
V
OUT
Figure 9 shows two interface options using the T2PSE
pin and the opto-isolator. The T2PSE pin is active low and
connects to an opt-isolater to communicate across the
DC/DC converter isolation barrier. The pull up resistor R
P
is sized according to the requirements of the opto-isolator
operating current, the pull-down capability of the T2PSE
pin, and the choice of V
+
. V
+
for example can come from
the PoE supply rail (which the LTC4265 GND is tied to), or
from the voltage source that supplies power to the DC/DC
converter. Option 1 has the advantage of not drawing power
unless T2PSE is declared active.
T2PSE Interface
When a 2-event Classifi cation sequence successfully
completes, the LTC4265 recognizes this sequence, and
provides an indicator bit, declaring the presence of a
Type-2 PSE. The open drain output provides the option
to use this signal to communicate to the LTC4265 load,
or to leave the pin unconnected.