Datasheet

LTM8032
7
8032fg
For more information www.linear.com/LTM8032
pin FuncTions
V
IN
(Bank 3): The V
IN
pin supplies current to the LTM8032’s
internal regulator and to the internal power switch. This
pin must be locally bypassed with an external, low ESR
capacitor of at least 2.2µF.
FIN (K3, L3): Filtered Input. This is the node after the input
EMI filter. Use this only if there is a need to modify the
behavior of the integrated EMI filter or if V
IN
rises or falls
rapidly; otherwise, leave these pins unconnected. See the
Applications Information section for more details.
GND (Bank 2): Tie these GND pins to a local ground plane
below the LTM8032 and the circuit components. In most
applications, the bulk of the heat flow out of the LTM8032
is through these pads, so the printed circuit design has a
large impact on the thermal performance of the part. See
the PCB Layout and Thermal Considerations sections for
more details. Return the feedback divider (R
ADJ
) to this net.
V
OUT
(Bank 1): Power Output Pins. Apply the output filter
capacitor and the output load between these pins and
GND pins.
AUX (Pin H5): Low Current Voltage Source for BIAS. The
AUX pin is internally connected
to V
OUT
and is placed
adjacent to the BIAS pin to ease printed circuit board
routing. Although this pin is internally connected to V
OUT
,
do not connect this pin to the load. If this pin is not tied
to BIAS, leave it floating.
BIAS (Pin H4): The BIAS pin connects to the internal power
bus. Connect to a power source greater than 2.8V. If the
output is greater than 2.8V, connect this pin to AUX. If
the output voltage is less, connect this to a voltage source
between 2.8V and 25V. Also, make sure that BIAS + V
IN
is less than 56V.
RUN/SS (Pin L5): Pull RUN/SS pin to less than 0.2V to
shut down the LTM8032. Tie to 2.5V or more for normal
operation. If the shutdown feature is not used, tie this pin
to the V
IN
pin. RUN/SS also provides a soft-start function;
see the Applications Information section.
RT (Pin G7): The RT pin is used to program the switching
frequency of the LTM8032 by connecting a resistor from
this pin to ground. The Applications Information section of
the data sheet includes a table to determine the resistance
value based on
the desired switching frequency. Minimize
capacitance at this pin.
SHARE (Pin H7): Tie this to the SHARE pin of another
LTM8032 when paralleling the outputs. Otherwise, do not
connect (leave floating).
SYNC (Pin L6): This is the external clock synchronization
input. Ground this pin for low ripple Burst Mode
®
operation
at low output loads. Tie to a stable voltage source greater
than 0.7V to disable Burst Mode operation. Do not leave
this pin floating. Tie to a clock source for synchronization.
Clock edges should have rise and fall times faster than 1µs.
See synchronization section in Applications Information.
PGOOD (Pin K7): The PGOOD pin is the open-collector
output of an internal comparator. PGOOD remains low until
the ADJ pin is within 10% of the final regulation voltage.
The PGOOD output is valid when V
IN
is above 3.6V and
RUN/SS is high. If this function is not used, leave this
pin floating.
ADJ (Pin J7): The LTM8032 regulates its ADJ pin to 0.79V.
Connect the adjust resistor from this pin to ground. The
value of R
ADJ
is given by the equation:
R
ADJ
=
196.71
V
OUT
–0.79
where R
ADJ
is in kΩ.