Datasheet

LTC2452
9
2452fd
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applicaTions inForMaTion
Figure 4. Data Output Timing
D
15
LSB
SDO
SCK
D
14
D
13
D
12
D
11
D
10
D
9
D
8
D
7
D
6
D
5
D
4
D
3
D
2
D
0
D
1
2452 F04
t
1
t
3
t
KQ
t
lSCK
t
hSCK
t
2
CS
MSB
with the most significant bit of the result being present at
the SDO output pin (SDO = D15) once CS goes low. A new
data bit appears at the SDO output pin after each falling
edge detected at the SCK input pin. The output data can be
reliably latched by the user using the rising edge of SCK.
Conversion Status Monitor
For certain applications, the user may wish to monitor
the LTC2452 conversion status. This can be achieved
by holding SCK HIGH during the conversion cycle. In
this condition, whenever the CS input pin is pulled low
(CS = LOW), the
SDO output pin will provide an indication
of the conversion status. SDO = HIGH is an indication of
a conversion cycle in progress while SDO = LOW is an
indication of a completed conversion cycle. An example
of such a sequence is shown in Figure 5.
Conversion status monitoring, while possible, is not re
-
quired for LTC2452 as its conversion time is fixed and equal
at approximately 16.6ms (23ms maximum). Therefore,
external timing can be used to determine the completion of a
conversion cycle.
S
ERIAL INTERFACE
The LTC2452 transmits the conversion result and receives
the start of conversion command through a synchronous
3-wire
interface. This interface can be used during the
CONVER
T and SLEEP states to assess the conversion
status and
during the D
ATA OUTPUT state to read the
conversion result, and to trigger a new conversion.
Serial Interface Operation Modes
The modes of operation can be summarized as follows:
1)
The LTC2452 functions with SCK idle high (commonly
known as CPOL = 1) or idle low (commonly known as
CPOL = 0).
Figure 5. Conversion Status Monitoring Mode
SLEEP
t
1
t
2
SDO
SCK = HIGH
CONVERT
2452 F05
CS