Datasheet

LTC2452
15
2452fd
For more information www.linear.com/LTC2452
applicaTions inForMaTion
A 0.1µF, high quality, ceramic capacitor in parallel with a
10µF ceramic capacitor should be connected between the
REF and GND pins, as close as possible to the package.
The 0.1µF capacitor should be placed closest to the ADC.
Driving V
IN
+
and V
IN
–
The input drive requirements can best be analyzed using
the equivalent circuit of Figure 16. The input signal V
SIG
is
connected to the ADC input pins (IN
+
and IN
–
) through an
equivalent source resistance R
S
. This resistor includes both
the actual generator source resistance and any additional
optional resistors connected to the input pins. Optional
input capacitors C
IN
are also connected to the ADC input
pins. This capacitor is placed in parallel with the ADC
input parasitic capacitance C
PAR
. Depending on the PCB
layout, C
PAR
has typical values between 2pF and 15pF. In
addition, the equivalent circuit of Figure 16 includes the
converter equivalent internal resistor R
SW
and sampling
capacitor C
EQ
.
There are some immediate trade-offs in R
S
and C
IN
without
needing a full circuit analysis. Increasing R
S
and C
IN
can
give the following benefits:
1) Due to the LTC2452’s input sampling algorithm, the input
current
drawn by either V
IN
+
or V
IN
–
over a conversion
cycle is typically 50nA. A high R
S
• C
IN
attenuates the
high frequency components of the input current, and
R
S
values up to 1k result in <1LSB error.
Figure 16. LTC2452 Input Drive Equivalent Circuit
2) The bandwidth from V
SIG
is reduced at the input pins
(IN
+
, IN
–
). This bandwidth reduction isolates the ADC
from high frequency signals, and as such provides
simple anti-aliasing and input noise reduction.
3) Switching transients generated by the ADC are attenu
-
ated before they go back to the signal source.
4)
A large C
IN
gives a better AC ground at the input pins,
helping reduce reflections back to the signal source.
5) Increasing R
S
protects the ADC by limiting the current
during an outside-the-rails fault condition.
There is a limit to how large R
S
• C
IN
should be for a given
application. Increasing R
S
beyond a given point increases
the voltage drop across R
S
due to the input current,
to the point that significant measurement errors exist.
Additionally, for
some applications, increasing the R
S
• C
IN
product too much may unacceptably attenuate the signal
at frequencies of interest.
For
most applications, it is desirable to implement C
IN
as
a high-quality 0.1µF ceramic capacitor and R
S
≤ 1k. This
capacitor should be located as close as possible to the
actual V
IN
package pin. Furthermore, the area encompassed
by this circuit path, as well as the path length, should be
minimized.
I
LEAK
I
LEAK
R
SW
15k
(TYP)
I
CONV
C
IN
IN
+
V
CC
SIG
+
SIG
–
R
S
C
EQ
0.35pF
(TYP)
C
PAR
+
–
2452 F16
I
LEAK
I
LEAK
R
SW
15k
(TYP)
I
CONV
C
IN
IN
–
V
CC
R
S
C
EQ
0.35pF
(TYP)
C
PAR
+
–