Datasheet

LTC2452
11
2452fd
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applicaTions inForMaTion
based upon external timing. The user then pulls CS low
(CS = ↓) and
uses 16 clock cycles to transfer the result.
Following the 16th rising edge of the clock, CS is pulled high
(CS = ↑), which triggers a new conversion.
The
timing
diagram in Figure 9 is identical to that of Figure 8,
except in this case a new conversion is triggered by SCK.
The 16th SCK falling edge triggers a new conversion cycle
and the CS signal is subsequently pulled high.
Examples of Aborting Cycle Using CS
For some applications, the user may wish to abort the I/O
cycle and begin a new conversion. If the LTC2452 is in
the data output state, a CS rising edge clears the remain
-
ing data bits from the output registers, aborts the output
cycle
and triggers a new conversion. Figure 10 shows
an example of aborting an I/O with idle-high (CPOL = 1)
and Figure 11 shows an example of aborting an I/O with
idle-low (CPOL = 0).
A new conversion cycle can be triggered using the CS
signal without having to generate any serial clock pulses
as shown in Figure 12. If SCK is maintained at a low logic
level, after the
end of a conversion cycle, a new conver-
sion
operation
can be triggered by pulling CS low and
then high. When CS is pulled low (CS = LOW), SDO will
output the sign (D15) of the result of the just completed
conversion. While a low logic level is maintained at SCK
Figure 9. Idle-Low (CPOL = 0) Clock. The 16th SCK Falling Edge Triggers a New Conversion
Figure 8. Idle-Low (CPOL = 0) Clock. CS Triggers a New Conversion
D
15
D
14
D
13
D
12
D
2
D
1
D
0
clk
1
clk
2
clk
3
clk
4
clk
14
clk
15
clk
16
SCK
SD0
CONVERT CONVERTSLEEP DATA OUTPUT
2452 F08
CS
D
15
D
14
D
13
D
12
D
2
D
1
D
0
SD0
clk
1
clk
2
clk
3
clk
4
clk
15
clk
14
clk
16
SCK
CONVERT CONVERTSLEEP DATA OUTPUT
2452 F09
CS