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LTC2258-12

LTC2257-12/LTC2256-12

225812fd

For more information www.linear.com/LTC2258-12

Typical applicaTion

FeaTures

applicaTions

DescripTion

12-Bit, 65/40/25Msps

Ultralow Power 1.8

V ADCs

Communications

Cellular Base Stations

Software Defined Radios

Portable Medical Imaging

Multi-Channel Data Acquisition

Nondestructive Testing

L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear

Technology Corporation. All other trademarks are the property of their respective owners.

71.1dB SNR

88dB SFDR

Low Power: 79mW/47mW/34mW

Single 1.8V Supply

CMOS, DDR CMOS or DDR LVDS Outputs

Selectable Input Ranges: 1V

P-P

to 2V

P-P

800MHz Full-Power Bandwidth S/H

Optional Data Output Randomizer

Optional Clock Duty Cycle Stabilizer

Shutdown and Nap Modes

Serial SPI Port for Configuration

Pin Compatible 14-Bit and 12-Bit Versions

40-Pin (6mm × 6mm) QFN Package

The LT C

2258-12/LTC2257-12/LTC2256-12 are sam-

pling 12-bit A/D

converters designed for digitizing high

frequency, wide dynamic range signals. They are perfect

for demanding communications applications with AC

performance that includes 71.1dB SNR and 88dB spurious

free dynamic range (SFDR). Ultralow jitter of 0.17ps

RMS

allows undersampling of IF frequencies with excellent

noise performance.

DC specs include ±0.3LSB INL (typical), ±0.1LSB DNL

(typical) and no missing codes over temperature. The

transition noise is a low 0.3LSB

RMS

The digital outputs can be either full rate CMOS, double

data rate CMOS, or double data rate LVDS. A separate

output power supply

allows the CMOS output swing to

range from 1.2V to 1.8V.

The ENC

and ENC

–

inputs may be driven differentially

or single-ended with a sine wave, PECL, LVDS, TTL or

CMOS inputs. An optional clock duty cycle stabilizer al

lows high performance at full speed for a wide range of

clock duty cycles.

LTC2258-12 2-Tone FFT,

= 68MHz and 69MHz

–

INPUT

S/H

CORRECTION

LOGIC

OUTPUT

DRIVERS

12-BIT

PIPELINED

ADC CORE

CLOCK/DUTY

CYCLE

CONTROL

D11

•

65MHz

CLOCK

ANALOG

INPUT

225812 TA01a

CMOS

LVDS

1.2V

TO 1.8V

1.8V

OGND

GND

FREQUENCY (MHz)

–100

–110

–120

–70

–60

–80

–90

AMPLITUDE (dBFS)

–50

–30

–40

–20

–10

20 30

225812 TA01b

Summary of content (34 pages)

PAGE 1
LTC2258-12 LTC2257-12/LTC2256-12 12-Bit, 65/40/25Msps Ultralow Power 1.8V ADCs Features n n n n n n n n n n n n n Description 71.1dB SNR 88dB SFDR Low Power: 79mW/47mW/34mW Single 1.
PAGE 2
LTC2258-12 LTC2257-12/LTC2256-12 Absolute Maximum Ratings (Notes 1, 2) Supply Voltages (VDD, OVDD)........................ –0.3V to 2V Analog Input Voltage (AIN+, AIN –, PAR/SER, SENSE) (Note 3)........... –0.3V to (VDD + 0.2V) Digital Input Voltage (ENC+, ENC–, CS, SDI, SCK) (Note 4)..................................... –0.3V to 3.9V SDO (Note 4).............................................. –0.3V to 3.9V Digital Output Voltage................. –0.3V to (OVDD + 0.
PAGE 3
LTC2258-12 LTC2257-12/LTC2256-12 Order Information LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE LTC2258CUJ-12#PBF LTC2258CUJ-12#TRPBF LTC2258UJ-12 40-Lead (6mm × 6mm) Plastic QFN 0°C to 70°C LTC2258IUJ-12#PBF LTC2258IUJ-12#TRPBF LTC2258UJ-12 40-Lead (6mm × 6mm) Plastic QFN –40°C to 85°C LTC2257CUJ-12#PBF LTC2257CUJ-12#TRPBF LTC2257UJ-12 40-Lead (6mm × 6mm) Plastic QFN 0°C to 70°C LTC2257IUJ-12#PBF LTC2257IUJ-12#TRPBF LTC2257UJ-12 40-Lead (6mm × 6m
PAGE 4
LTC2258-12 LTC2257-12/LTC2256-12 Analog Input The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS VIN Analog Input Range (AIN+ – AIN–) 1.7V < VDD < 1.9V l VIN(CM) Analog Input Common Mode (AIN+ + AIN–)/2 Differential Analog Input (Note 8) l VCM – 100mV VCM VCM + 100mV V VSENSE External Voltage Reference Applied to SENSE External Reference Mode l 0.
PAGE 5
LTC2258-12 LTC2257-12/LTC2256-12 Digital Inputs And Outputs The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS ENCODE INPUTS (ENC+, ENC– ) Differential Encode Mode (ENC– Not Tied to GND) VID Differential Input Voltage (Note 8) l 0.2 VICM Common Mode Input Voltage Internally Set Externally Set (Note 8) l 1.1 l 0.2 V 1.2 1.6 V V 3.
PAGE 6
LTC2258-12 LTC2257-12/LTC2256-12 Power Requirements The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 9) LTC2258-12 SYMBOL PARAMETER CONDITIONS LTC2257-12 LTC2256-12 MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 V 1.9 1.1 1.9 1.1 1.9 V 21 mA mA CMOS Output Modes: Full Data Rate and Double Data Rate VDD Analog Supply Voltage (Note 10) l 1.
PAGE 7
LTC2258-12 LTC2257-12/LTC2256-12 timing characteristics The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Digital Data Outputs (LVDS Mode) tD ENC to Data Delay CL = 5pF (Note 8) l 1.1 1.8 3.2 ns tC ENC to CLKOUT Delay CL = 5pF (Note 8) l 1 1.5 2.7 ns tSKEW DATA to CLKOUT Skew tD – tC (Note 8) l 0 0.3 0.6 ns Pipeline Latency 5.
PAGE 8
LTC2258-12 LTC2257-12/LTC2256-12 Timing Diagrams Full-Rate CMOS Output Mode Timing All Outputs Are Single-Ended and Have CMOS Levels tAP ANALOG INPUT N+4 N+2 N N+3 tH tL N+1 ENC– ENC+ tD N–5 D0-D11, OF N–4 N–3 N–2 N–1 tC CLKOUT + CLKOUT – 225812 TD01 Double Data Rate CMOS Output Mode Timing All Outputs Are Single-Ended and Have CMOS Levels tAP ANALOG INPUT N+4 N+2 N N+3 tH tL N+1 ENC– ENC+ tD D0_1 tD D0N-5 D1N-5 D0N-4 D1N-4 D0N-3 D1N-3 D0N-2 D1N-2 D10N-5 D11N-5 D10N-4 D11
PAGE 9
LTC2258-12 LTC2257-12/LTC2256-12 timing DIAGRAMS Double Data Rate LVDS Output Mode Timing All Outputs Are Differential and Have LVDS Levels tAP N+4 N+2 N ANALOG INPUT N+3 tH tL N+1 ENC– ENC+ tD D0_1+ D0_1– tD D0N-5 D1N-5 D0N-4 D1N-4 D0N-3 D1N-3 D0N-2 D1N-2 D10N-5 D11N-5 D10N-4 D11N-4 D10N-3 D11N-3 D10N-2 D11N-2 •• • D10_11+ D10_11– OF+ OFN-5 OF– OFN-4 OFN-3 tC tC CLKOUT+ OFN-3 CLKOUT – 225812 TD03 SPI Port Timing (Readback Mode) tDS tS tDH tSCK tH CS SCK tDO SDI SDO
PAGE 10
LTC2258-12 LTC2257-12/LTC2256-12 Typical Performance Characteristics LTC2258-12: Integral Nonlinearity (INL) LTC2258-12: Differential Nonlinearity (DNL) 1.0 0 0.8 0.8 –10 0.6 0.6 0.4 0.4 0.2 0 –0.2 –0.4 0 –0.2 –0.4 –0.6 –0.8 –0.8 –1.0 –1.0 1024 2048 3072 OUTPUT CODE 4096 –30 0.2 –0.6 0 –20 AMPLITUDE (dBFS) DNL ERROR (LSB) INL ERROR (LSB) 1.
PAGE 11
LTC2258-12 LTC2257-12/LTC2256-12 Typical Performance Characteristics LTC2258-12: SFDR vs Input Frequency, –1dB, 2V Range, 65Msps 110 100 85 80 75 50 dBFS 90 SFDR (dBc AND dBFS) SFDR (dBFS) 90 LTC2258-12: IVDD vs Sample Rate, 5MHz Sine Wave Input, –1dB LVDS OUTPUTS 45 80 70 dBc 60 IVDD (mA) 95 LTC2258-12: SFDR vs Input Level, fIN = 70MHz, 2V Range, 65Msps 50 CMOS OUTPUTS 40 30 35 20 70 40 10 65 0 50 0 –80 –70 –60 –50 –40 –30 –20 –10 INPUT LEVEL (dBFS) 100 150 200 250 300 350 INPUT FR
PAGE 12
LTC2258-12 LTC2257-12/LTC2256-12 Typical Performance Characteristics 0 0 –10 –20 –20 –20 –30 –30 –30 –40 –50 –60 –70 –80 AMPLITUDE (dBFS) –10 –40 –50 –60 –70 –80 –40 –50 –60 –70 –80 –90 –100 –90 –100 –90 –100 –110 –120 –110 –120 –110 –120 0 20 10 FREQUENCY (MHz) 0 16000 14000 SNR (dBFS) 10000 8000 72 95 71 90 70 85 69 68 6000 4000 67 2000 2051 OUTPUT CODE 66 2053 0 50 100 150 200 250 300 INPUT FREQUENCY (MHz) LTC2257-12: SFDR vs Input Level, fIN = 70MHz, 2V Range, 40M
PAGE 13
LTC2258-12 LTC2257-12/LTC2256-12 Typical Performance Characteristics LTC2256-12: Integral Nonlinearity (INL) 72 71 INL ERROR (LSB) SNR (dBFS) 70 69 68 67 66 0.6 0.7 0.8 0.9 1 1.1 SENSE PIN (V) 1.2 1.0 1.0 0.8 0.8 0.6 0.6 0.4 0.4 0.2 0 –0.2 –0.4 –0.2 –0.4 –0.6 –0.8 0 1024 2048 3072 OUTPUT CODE –1.
PAGE 14
LTC2258-12 LTC2257-12/LTC2256-12 Typical Performance Characteristics LTC2256-12: SNR vs Input Frequency, –1dB, 2V Range, 25Msps LTC2256-12: SFDR vs Input Frequency, –1dB, 2V Range, 25Msps 72 95 71 90 70 85 110 LTC2256-12: SFDR vs Input Level, fIN = 70MHz, 2V Range, 25Msps 69 68 80 75 67 70 66 65 dBFS 90 SFDR (dBc AND dBFS) SFDR (dBFS) SNR (dBFS) 100 80 70 dBc 60 50 40 30 20 10 0 50 100 150 200 250 300 INPUT FREQUENCY (MHz) 350 0 50 0 –80 –70 –60 –50 –40 –30 –20 –10 INPUT LEVEL (
PAGE 15
LTC2258-12 LTC2257-12/LTC2256-12 Pin Functions Pins That Are the Same for All Digital Output Modes AIN+ (Pin 1): Positive Differential Analog Input. AIN– (Pin 2): Negative Differential Analog Input. GND (Pin 3): ADC Power Ground. REFH (Pins 4, 5): ADC High Reference. Bypass to Pins 6, 7 with a 2.2µF ceramic capacitor and to ground with a 0.1µF ceramic capacitor. REFL (Pins 6, 7): ADC Low Reference. Bypass to Pins 4, 5 with a 2.2µF ceramic capacitor and to ground with a 0.1µF ceramic capacitor.
PAGE 16
LTC2258-12 LTC2257-12/LTC2256-12 Pin Functions Full-Rate CMOS Output Mode Double Data Rate LVDS Output Mode All Pins Below Have CMOS Output Levels (OGND to OVDD) All Pins Below Have LVDS Output Levels. The Output Current Level is Programmable. There is an Optional Internal 100Ω Termination Resistor Between the Pins of Each LVDS Output Pair. D0 to D11 (Pins 19-24, 29-34): Digital Outputs. D11 is the MSB. CLKOUT– (Pin 27): Inverted version of CLKOUT+. CLKOUT+ (Pin 28): Data Output Clock.
PAGE 17
LTC2258-12 LTC2257-12/LTC2256-12 Functional Block Diagram AIN+ AIN– VCM INPUT S/H FIRST PIPELINED ADC STAGE SECOND PIPELINED ADC STAGE THIRD PIPELINED ADC STAGE FOURTH PIPELINED ADC STAGE VDD FIFTH PIPELINED ADC STAGE GND VDD/2 0.1µF VREF 1µF 1.25V REFERENCE SHIFT REGISTER AND CORRECTION RANGE SELECT SENSE REFH REF BUF REFL INTERNAL CLOCK SIGNALS OVDD OF DIFF REF AMP MODE CONTROL REGISTERS CLOCK/DUTY CYCLE CONTROL • • • OUTPUT DRIVERS D11 D0 CLKOUT + CLKOUT – REFH 0.
PAGE 18
LTC2258-12 LTC2257-12/LTC2256-12 Applications Information CONVERTER OPERATION ANALOG INPUT The LTC2258-12/LTC2257-12/LTC2256-12 are low power 12-bit 65Msps/40Msps/25Msps A/D converters that are powered by a single 1.8V supply. The analog inputs should be driven differentially. The encode input can be driven differentially or single-ended for lower power consumption.
PAGE 19
LTC2258-12 LTC2257-12/LTC2256-12 Applications Information INPUT DRIVE CIRCUITS Transformer Coupled Circuits Input filtering Figure 3 shows the analog input being driven by an RF transformer with a center-tapped secondary. The center tap is biased with VCM, setting the A/D input at its optimal DC level. At higher input frequencies a transmission line balun transformer (Figures 4 to 6) has better balance, resulting in lower A/D distortion.
PAGE 20
LTC2258-12 LTC2257-12/LTC2256-12 Applications Information Amplifier Circuits LTC2258-12 Figure 7 shows the analog input being driven by a high speed differential amplifier. The output of the amplifier is AC coupled to the A/D so the amplifier’s output common mode voltage can be optimally set to minimize distortion. At very high frequencies an RF gain block will often have lower distortion than a differential amplifier.
PAGE 21
LTC2258-12 LTC2257-12/LTC2256-12 Applications Information Encode Input The signal quality of the encode inputs strongly affects the A/D noise performance. The encode inputs should be treated as analog signals—do not route them next to digital traces on the circuit board. There are two modes of operation for the encode inputs: the differential encode mode (Figure 10) and the single-ended encode mode (Figure 11).
PAGE 22
LTC2258-12 LTC2257-12/LTC2256-12 Applications Information by mode control register A2 (serial programming mode), or by CS (parallel programming mode). For applications where the sample rate needs to be changed quickly, the clock duty cycle stabilizer can be disabled. If the duty cycle stabilizer is disabled, care should be taken to make the sampling clock have a 50%(±5%) duty cycle. The duty cycle stabilizer should not be used below 5Msps.
PAGE 23
LTC2258-12 LTC2257-12/LTC2256-12 Applications Information Phase Shifting the Output Clock DATA FORMAT In full-rate CMOS mode the data output bits normally change at the same time as the falling edge of CLKOUT+, so the rising edge of CLKOUT+ can be used to latch the output data. In double data rate CMOS and LVDS modes the data output bits normally change at the same time as the falling and rising edges of CLKOUT+.
PAGE 24
LTC2258-12 LTC2257-12/LTC2256-12 Applications Information Digital Output Randomizer Alternate Bit Polarity Interference from the A/D digital outputs is sometimes unavoidable. Digital interference may be from capacitive or inductive coupling or coupling through the ground plane. Even a tiny coupling factor can cause unwanted tones in the ADC output spectrum. By randomizing the digital output before it is transmitted off chip, these unwanted tones can be randomized which reduces the unwanted tone amplitude.
PAGE 25
LTC2258-12 LTC2257-12/LTC2256-12 Applications Information The digital output is decoded at the receiver by inverting the odd bits (D1, D3, D5, D7, D9, D11). The alternate bit polarity mode is independent of the digital output randomizer—either, both or neither function can be on at the same time. When alternate bit polarity mode is on, the data format is offset binary and the 2’s complement control bit has no effect.
PAGE 26
LTC2258-12 LTC2257-12/LTC2256-12 Applications Information Serial Programming Mode To use the serial programming mode, PAR/SER should be tied to ground. The CS, SCK, SDI and SDO pins become a serial interface that program the A/D mode control registers. Data is written to a register with a 16-bit serial word. Data can also be read back from a register to verify its contents. Serial data transfer starts when CS is taken low. The data on the SDI pin is latched at the first 16 rising edges of SCK.
PAGE 27
LTC2258-12 LTC2257-12/LTC2256-12 Applications Information REGISTER A2: TIMING REGISTER (ADDRESS 02h) D7 X D6 D5 D4 D3 D2 D1 D0 X X X CLKINV CLKPHASE1 CLKPHASE0 DCS Bits 7-4 Unused, Don’t Care Bits.
PAGE 28
LTC2258-12 LTC2257-12/LTC2256-12 Applications Information REGISTER A4: DATA FORMAT REGISTER (ADDRESS 04h) D7 X D6 D5 D4 D3 D2 D1 D0 X OUTTEST2 OUTTEST1 OUTTEST0 ABP RAND TWOSCOMP Bit 7-6 Unused, Don’t Care Bits. Bits 5-3 OUTTEST2:OUTTEST0 Digital Output Test Pattern Bits 000 = Digital Output Test Patterns Off 001 = All Digital Outputs = 0 011 = All Digital Outputs = 1 101 = Checkerboard Output Pattern.
PAGE 29
LTC2258-12 LTC2257-12/LTC2256-12 Typical Applications LTC2258 Schematic T2 MABAES0060 • R9 10Ω • SENSE R39 33.2Ω 1% ANALOG INPUT R10 10Ω R40 33.2Ω 1% C23 1µF R14 1k C51 4.7pF C17 1µF R16 100Ω R15 100Ω C12 0.1µF VDD C13 1µF C19 0.1µF 40 39 38 37 VDD SENSE VREF VCM R27 10Ω 1 R28 10Ω 2 3 4 C15 0.1µF C20 2.2µF 5 6 7 C21 0.1µF VDD PAR/SER 8 9 10 C18 0.
PAGE 30
LTC2258-12 LTC2257-12/LTC2256-12 TYPICAL APPLICATIONS Silkscreen Top Top Side 225812 TA04 225812 TA03 Inner Layer 2 GND Inner Layer 3 225812 TA05 30 225812 TA06 225812fd For more information www.linear.
PAGE 31
LTC2258-12 LTC2257-12/LTC2256-12 TYPICAL APPLICATIONS Inner Layer 4 Inner Layer 5 Power 225812 TA07 225812 TA08 Bottom Side 225812 TA09 225812fd For more information www.linear.
PAGE 32
LTC2258-12 LTC2257-12/LTC2256-12 Package Description Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. UJ Package 40-Lead Plastic QFN (6mm × 6mm) (Reference LTC DWG # 05-08-1728 Rev Ø) 0.70 ±0.05 6.50 ±0.05 5.10 ±0.05 4.42 ±0.05 4.50 ±0.05 (4 SIDES) 4.42 ±0.05 PACKAGE OUTLINE 0.25 ±0.05 0.50 BSC RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED 6.00 ± 0.10 (4 SIDES) 0.75 ± 0.05 R = 0.10 TYP R = 0.
PAGE 33
LTC2258-12 LTC2257-12/LTC2256-12 Revision History REV DATE DESCRIPTION B 08/12 Corrected IOVDD to IOVDD (Revision history begins at Rev B) PAGE NUMBER 11, 12, 14 Corrected RESET REGISTER A0, D7 description 25 Attached VDD to pins 9, 10 and 40 on schematic 28 C 1/13 Updated column headings under Converter Characteristics to the correct part numbers. 3 D 1/14 Corrected "external reference” to "internal reference” for 1V input range.
PAGE 34
LTC2258-12 LTC2257-12/LTC2256-12 Related Parts PART NUMBER DESCRIPTION COMMENTS LT1993-2 High Speed Differential Op Amp 800MHz BW, 70dBc Distortion at 70MHz, 6dB Gain LT1994 Low Noise, Low Distortion Fully Differential Input/ Output Amplifier/Driver Low Distortion: –94dBc at 1MHz LTC2202 16-Bit, 10Msps, 3.3V ADC, Lowest Noise 140mW, 81.6dB SNR, 100dB SFDR, 48-Pin QFN LTC2203 16-Bit, 25Msps, 3.3V ADC, Lowest Noise 220mW, 81.6dB SNR, 100dB SFDR, 48-Pin QFN LTC2204 16-Bit, 40Msps, 3.