Datasheet

LTC2309
15
2309fd
AppLICAtIOns InFORMAtIOn
the ADC is addressed during a conversion, it will not
acknowledge R/W requests and will issue a NACK by
leaving the SDA line HIGH. If the conversion is com-
plete, the LTC2309 issues an ACK by pulling the SDA
line LOW. The LTC2309 has two registers. The 12-bit
wide output register contains the last conversion result.
The 6-bit wide input register configures the input MUX
and the operating mode of the ADC.
Output Data Format
The output register contains the last conversion result.
After each conversion is completed, the device auto-
matically enters either nap or sleep mode depending
on the setting of the SLP bit (see Nap Mode and Sleep
Mode sections). When the LTC2309 is addressed for
a read operation, it acknowledges by pulling SDA
LOW and acts as a transmitter. The master/receiver
can read up to two bytes from the LTC2309. After a
complete read operation of 2 bytes, a STOP condition
is needed to initiate a new conversion. The device will
NACK subsequent read operations while a conversion
is being performed.
The data output stream is 16 bits long and is shifted
out on the falling edges of SCL (see Figure 8a). The
first bit is the MSB and the 12th bit is the LSB of the
conversion result. The remaining four bits are zero.
Figures 14 and 15 are the transfer characteristics for
the bipolar and unipolar modes. Data is output on the
SDA line in 2’s complement format for bipolar readings
or in straight binary for unipolar readings.
1 2
A6SDA
START BY
MASTER
ACK BY
ADC
ACK BY
MASTER
NACK BY
MASTER
STOP
BY MASTER
CONVERSION
INITIATED
SCL
SCL
(CONTINUED)
A5 A4 A3 A2 A1 A0 R/W
3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
1 2 3 4 5 6 7 8 9
2309 F08a
B11 B10
READ 1 BYTE
B9 B8 B7
MOST SIGNIFICANT DATA BYTE
B6 B5 B4
• • •
• • •
SDA
(CONTINUED)
• • •
• • •
B3 B2 B1 B0
LEAST SIGNIFICANT DATA BYTE
READ 1 BYTE
ADDRESS FRAME
Figure 8a. Timing Diagram for Reading from the LTC2309