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LTC2309

2309fd

BLOCK DIAGRAM

FeAtuRes

AppLICAtIOns

DesCRIptIOn

8-Channel, 12-Bit SAR ADC

with I

C Interface

Industrial Process Control

Motor Control

Accelerometer Measurements

Battery-Operated Instruments

Isolated and/or Remote Data Acquisition

Power Supply Monitoring

Integral Nonlinearity

vs Output Code

12-Bit Resolution

Low Power: 1.5mW at 1ksps, 35µW Sleep Mode

14ksps Throughput Rate

Low Noise: SNR = 73.4dB

Guaranteed No Missing Codes

Single 5V Supply

2-Wire I

C Compatible Serial Interface with Nine

Addresses Plus One Global for Synchronization

Fast Conversion Time: 1.3µs

Internal Reference

Internal 8-Channel Multiplexer

Internal Conversion Clock

Unipolar or Bipolar Input Ranges (Software Selectable)

Guaranteed Operation from –40°C to 125°C

(TSSOP Package)

24-Pin 4mm × 4mm QFN and 20-Pin TSSOP Packages

The LTC

2309 is a low noise, low power, 8-channel, 12-bit

successive approximation ADC with an I

C compatible

serial interface. This ADC includes an internal reference

and a fully differential sample-and-hold circuit to reduce

common mode noise. The LTC2309 operates from an

internal clock to achieve a fast 1.3µs conversion time.

The LTC2309 operates from a single 5V supply and

draws just 300µA at a throughput rate of 1ksps. The

ADC enters nap mode when not converting, reducing

the power dissipation.

The LTC2309 is available in both a small 24-pin 4mm ×

4mm QFN and a 20-pin TSSOP package. The internal 2.5V

reference and 8-channel multiplexer further reduce PCB

board space requirements.

The low power consumption and small size make the

LTC2309 ideal for battery-operated and portable applica-

tions, while the 2-wire I

C compatible serial interface makes

this ADC a good match for space-constrained systems.

L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and

Easy Drive is a trademark of Linear Technology Corporation. All other trademarks are the

property of their respective owners.

CH0

CH1

CH2

CH3

CH4

CH5

CH6

CH7

COM

2309 TA01

PORT

ANALOG

INPUT

MUX

ANALOG INPUTS

0V TO 4.096V UNIPOLAR

±2.048V BIPOLAR

REFCOMP

INTERNAL

2.5V REF

GND

LTC2309

0.1µF

12-BIT

SAR ADC

–

2.2µF

10µF0.1µF

10µF

REF

SDA

SCL

AD1

AD0

OUTPUT CODE

INL (LSB)

0.25

0.50

4096

2309 G01

–0.25

–0.50

–1.00

1024

2048

3072

–0.75

1.00

0.75

Summary of content (26 pages)

PAGE 1
LTC2309 8-Channel, 12-Bit SAR ADC with I2C Interface Features n n n n n n n n n n n n n n Description 12-Bit Resolution Low Power: 1.5mW at 1ksps, 35µW Sleep Mode 14ksps Throughput Rate Low Noise: SNR = 73.4dB Guaranteed No Missing Codes Single 5V Supply 2-Wire I2C Compatible Serial Interface with Nine Addresses Plus One Global for Synchronization Fast Conversion Time: 1.
PAGE 2
LTC2309 Absolute Maximum Ratings (Notes 1, 2) Supply Voltage VDD........................................................... –0.3V to 6V Analog Input Voltage (Note 3) CH0-CH7, COM, VREF , REFCOMP..................... (GND – 0.3V) to (VDD + 0.3V) Digital Input Voltage (Note 3)............................. (GND – 0.3V) to (VDD + 0.3V) Digital Output Voltage....... (GND – 0.3V) to (VDD + 0.3V) Power Dissipation............................................... 500mW Operating Temperature Range LTC2309C...........
PAGE 3
LTC2309 CONVERTER AND MULTIPLEXER CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C.
PAGE 4
LTC2309 INTERNAL REFERENCE CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4) PARAMETER VREF Output Voltage VREF Output Tempco VREF Output Impedance VREFCOMP Output Voltage VREF Line Regulation CONDITIONS IOUT = 0 (QFN) IOUT = 0 (TSSOP) IOUT = 0 –0.1mA ≤ IOUT ≤ 0.1mA IOUT = 0 VDD = 4.75V to 5.25V l l MIN 2.47 2.46 TYP 2.50 2.50 ±25 8 4.096 0.8 MAX 2.53 2.
PAGE 5
LTC2309 I2C TIMING CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C.
PAGE 6
LTC2309 Typical Performance Characteristics TA = 25°C, VDD = 5V, fSMPL = 14ksps, unless otherwise noted. Differential Nonlinearity vs Output Code 1kHz Sine Wave 8192 Point FFT Plot 1.00 1.00 0 0.75 0.75 –20 0.50 0.50 0.25 0.25 0 –0.25 0 –0.25 –0.50 –0.50 –0.75 –0.75 –1.00 0 1024 2048 4096 3072 –1.00 –60 –80 –100 –120 0 1024 OUTPUT CODE 2048 4096 3072 –140 0 1 OUTPUT CODE 2309 G01 6 Full-Scale Error vs Temperature OFFSET ERROR (LSB) 0.5 FULL-SCALE ERROR (LSB) 1.5 2.
PAGE 7
LTC2309 Pin Functions (QFN) CH3-CH7 (Pins 1-5): Channel 3 to Channel 7 Analog Inputs. CH3-CH7 can be configured as single-ended or differential input channels. See the Analog Input Multiplexer section. AD1 (Pin 15): Chip Address Control Pin. This pin is configured as a three-state (LOW, HIGH, floating) address control bit for the device I2C address. See Table 2 for address selection. COM (Pin 6): Common Input. This is the reference point for all single-ended inputs.
PAGE 8
LTC2309 Pin Functions (TSSOP) REFCOMP (Pin 1): Reference Buffer Output. Bypass to GND with 10µF and 0.1µF ceramic capacitors in parallel. Nominal output voltage is 4.096V. The internal reference buffer driving this pin is disabled by grounding VREF , allowing REFCOMP to be overdriven by an external source. GND (Pins 2, 8 , 9): Ground. All GND pins must be connected to a solid ground plane. VDD (Pins 3, 10): 5V Supply. The range of VDD is 4.75V to 5.25V.
PAGE 9
LTC2309 FUNCTIONAL Block Diagram VDD LTC2309 CH0 AD1 AD0 CH1 CH2 CH3 CH4 ANALOG INPUT MUX + – I2C PORT 12-BIT SAR ADC SCL SDA CH5 CH6 CH7 INTERNAL 2.5V REF COM VREF 8k GAIN = 1.
PAGE 10
LTC2309 Applications Information Overview Programming the LTC2309 The LTC2309 is a low noise, 8-channel, 12-bit successive approximation register (SAR) A/D converter with an I2C compatible serial interface. The LTC2309 includes a precision internal reference and a configurable 8-channel analog input multiplexer (MUX). The ADC may be configured to accept single-ended or differential signals and can operate in either unipolar or bipolar mode.
PAGE 11
LTC2309 Applications Information 4 Differential + (–) – (+) { + (–) – (+) { CH0 CH1 + (–) – (+) { + (–) – (+) { CH4 CH5 8 Single-Ended + + + + + + + + CH2 CH3 CH6 CH7 1st Conversion CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 + –{ + –{ 2nd Conversion CH2 CH3 – + { CH2 CH3 CH4 CH5 + + { CH4 CH5 COM (UNUSED) COM (–) COM (–) 2328 F01b Figure 1b.
PAGE 12
LTC2309 Applications Information When using a filter with a large CFILTER value (e.g. 1µF), the inputs do not completely settle and the capacitive input switching currents are averaged into a net DC current (IDC). In this case, the analog input can be modeled by an equivalent resistance (REQ = 1/(fSMPL • CIN)) in series with an ideal voltage source (VREFCOMP/2), as shown in Figure 3b. The magnitude of the DC current is then approximately IDC = (VIN – VREFCOMP/2)/REQ, which is roughly proportional to VIN.
PAGE 13
LTC2309 Applications Information 0 –20 MAGNITUDE (dB) internal reference buffer can also be overdriven from 1V to VDD, as shown in Figure 6c. To do so, VREF must be grounded to disable the reference buffer. SNR = 73.4dB SINAD = 73.3dB THD = –88dB –40 –60 –80 2.5V BANDGAP REFERENCE 2.2µF –100 –120 –140 R1 8k VREF REFCOMP 4.096V 0 2 1 5 4 3 FREQUENCY (kHz) 6 7 REFERENCE AMP 10µF R2 0.1µF 2309 G03 GND Figure 5.
PAGE 14
LTC2309 Applications Information Internal Conversion Clock The START and STOP Conditions The internal conversion clock is factory trimmed to achieve a typical conversion time (tCONV) of 1.3μs and a maximum conversion time of 1.8μs over the full operating temperature range. Referring to Figure 7, a START (S) condition is generated by transitioning SDA from HIGH to LOW while SCL is HIGH. The bus is considered to be busy after the START condition.
PAGE 15
LTC2309 Applications Information the ADC is addressed during a conversion, it will not acknowledge R/W requests and will issue a NACK by leaving the SDA line HIGH. If the conversion is complete, the LTC2309 issues an ACK by pulling the SDA line LOW. The LTC2309 has two registers. The 12-bit wide output register contains the last conversion result. The 6-bit wide input register configures the input MUX and the operating mode of the ADC.
PAGE 16
LTC2309 Applications Information Input Data Format When the LTC2309 is addressed for a write operation, it acknowledges by pulling SDA LOW during the LOW period before the 9th cycle and acts as a receiver. The master/transmitter can then send 1 byte to program the device. The input byte consists of the 6-bit DIN word followed by two bits that are ignored by the ADC and are considered don’t cares (X) (see Figure 8b). The input bits are latched on the rising edge of SCL during the write operation.
PAGE 17
LTC2309 Applications Information Continuous Read In applications where the same input channel is sampled each cycle, conversions can be continuously performed and read without a write cycle (see Figure 9). The DIN word remains unchanged from the last value written into the device. If the device has not been written to since power-up, the DIN word defaults to all 0s (S/D = O/S = S0 = S1 = UNI = SLP = 0). At the end of a read operation, a STOP condition may be given to start a new conversion.
PAGE 18
LTC2309 Applications Information Synchronizing Multiple LTC2309s with a Global Address Call Nap Mode In applications where several LTC2309s or other I2C SAR ADCs from Linear Technology Corporation are used on the same I2C bus, all converters can be synchronized through the use of a global address call. Prior to issuing the global address call, all converters must have completed a conversion cycle. The master then issues a START, followed by the global address 1101011, and a write request.
PAGE 19
LTC2309 Applications Information If a write operation is being performed, acquisition of the input signal begins on the falling edge of the sixth clock cycle after the DIN word has been shifted in, as shown in Figure 13b. The LTC2309 will acquire the signal from the input channel that was most recently programmed by the DIN word. A minimum of 240ns is required to acquire the input signal before initiating a new conversion.
PAGE 20
LTC2309 Applications Information Board Layout and Bypassing To obtain the best performance, a printed circuit board with a solid ground plane is required. Layout for the printed board should ensure digital and analog signal lines are separated as much as possible. Care should be taken not to run any digital signals alongside an analog signal. All analog inputs should be shielded by GND. VREF , REFCOMP and VDD should be bypassed to the ground plane as close to the pin as possible.
PAGE 21
LTC2309 Applications Information 2309 F16b Figure 16b. Layer 1 Component Side Figure 16c.
PAGE 22
LTC2309 Applications Information Figure 16d. Layer 3 Power Plane 2309 F16d 2309 F16e Figure 16e.
PAGE 23
LTC2309 Package Description UF Package 24-Lead Plastic QFN (4mm × 4mm) (Reference LTC DWG # 05-08-1697) 0.70 ±0.05 4.50 ± 0.05 2.45 ± 0.05 3.10 ± 0.05 (4 SIDES) PACKAGE OUTLINE 0.25 ±0.05 0.50 BSC RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS 4.00 ± 0.10 (4 SIDES) BOTTOM VIEW—EXPOSED PAD R = 0.115 TYP 0.75 ± 0.05 PIN 1 NOTCH R = 0.20 TYP OR 0.35 s 45° CHAMFER 23 24 PIN 1 TOP MARK (NOTE 6) 0.40 ± 0.10 1 2 2.45 ± 0.10 (4-SIDES) (UF24) QFN 0105 0.200 REF 0.00 – 0.05 0.25 ± 0.05 0.50 BSC NOTE: 1.
PAGE 24
LTC2309 Package Description F Package 20-Lead Plastic TSSOP (4.4mm) (Reference LTC DWG # 05-08-1650) 6.40 – 6.60* (.252 – .260) 1.05 ±0.10 6.60 ±0.10 20 19 18 17 16 15 14 13 12 11 4.50 ±0.10 0.45 ±0.05 6.40 (.252) BSC 0.65 BSC 1 2 3 4 5 6 7 8 9 10 RECOMMENDED SOLDER PAD LAYOUT 4.30 – 4.50** (.169 – .177) 0.09 – 0.20 (.0035 – .0079) 0.25 REF 1.10 (.0433) MAX 0° – 8° 0.50 – 0.75 (.020 – .030) NOTE: 1. CONTROLLING DIMENSION: MILLIMETERS MILLIMETERS 2. DIMENSIONS ARE IN (INCHES) 0.65 (.
PAGE 25
LTC2309 Revision History REV DATE DESCRIPTION D 7/10 Revised Block Diagram (Revision history begins at Rev D) PAGE NUMBER Changed AVDD and DVDD pins to VDD only Revised Note 2 1 2, 4-9, 20 5 Consolidated AVDD and DVDD into VDD and revised VREF and REFCOMP pin descriptions in Pin Functions section Revised Figures 6b and 6c and Internal Reference paragraph, and added text to I2C Interface in Applications Information section 7, 8 13, 14 Changed NAK to NACK in Figure 8a 15 Revised Typical Applicati
PAGE 26
LTC2309 Typical Application Driving the LTC2309 with ±10V Input Signals Using a Precision Attenuator 5V IN OUT LT1790-2.5 0.1µF 1µF GND 10V 5V 7 8 450k 50k 9 150k 10 10µF – 450k + 1 450k 4pF 3 47pF 450k 2 150k ±10V INPUT SIGNAL 6 100Ω LT1991 0.1µF AD1 AD0 VDD CH0 CH3 4pF 4 CH4 5 –10V 1.7k LTC2309 CH1 CH2 50k 1.7k ANALOG INPUT MUX + – I2C PORT 12-BIT SAR ADC SCL CONTROL LOGIC (FPGA, CPLD, DSP, ETC) SDA CH5 CH6 INTERNAL 2.5V REF CH7 COM GND VREF 2.2µF REFCOMP 0.