Datasheet

LTC4269-1
24
42691fc
in sensed output voltage, compensating for the IR drops.
Assuming relatively fi xed power supply effi ciency, Eff,
power balance gives:
P
OUT
= Eff • P
IN
V
OUT
• I
OUT
= Eff • V
IN
• I
IN
Average primary-side current is expressed in terms of
output current as follows:
I
IN
=K1•I
OUT
where:
K1=
V
OUT
V
IN
•Eff
So, the effective change in V
OUT
target is:
ΔV
OUT
=K1•
R
SENSE
R
CMP
•R1•N
SF
• ΔI
OUT
thus:
ΔV
OUT
ΔI
OUT
=K1•
R
SENSE
R
CMP
•R1•N
SF
where:
K1 = dimensionless variable related to V
IN
, V
OUT
and ef-
fi ciency, as previously explained
R
SENSE
= external sense resistor
Nominal output impedance cancellation is obtained by
equating this expression with R
S(OUT)
:
K1•
R
SENSE
R
CMP
•R1•N
SF
=
ESR+R
DS(ON)
1−DC
Solving for R
CMP
gives:
R
CMP
=K1•
R
SENSE
•1−DC
()
ESR+R
DS(ON)
•R1•N
SF
The practical aspects of applying this equation to determine
an appropriate value for the R
CMP
resistor are discussed
subsequently in the Applications Information section.
Transformer Design
Transformer design/specifi cation is the most critical part of
a successful application of the LTC4269-1. The following
sections provide basic information about designing the
transformer and potential trade-offs. If you need help, the
LTC Applications group is available to assist in the choice
and/or design of the transformer.
Turns Ratios
The design of the transformer starts with determining
duty cycle (DC). DC impacts the current and voltage stress
on the power switches, input and output capacitor RMS
currents and transformer utilization (size vs power). The
ideal turns ratio is:
N
IDEAL
=
V
OUT
V
IN
•
1−DC
DC
Avoid extreme duty cycles, as they generally increase cur-
rent stresses. A reasonable target for duty cycle is 50%
at nominal input voltage.
For instance, if we wanted a 48V to 5V converter at 50%
DC then:
N
IDEAL
=
5
48
•
1−0.5
0.5
=
1
9.6
In general, better performance is obtained with a lower
turns ratio. A DC of 45.5% yields a 1:8 ratio.
APPLICATIONS INFORMATION
•
•
•
MP
R
CMPF
50k
V
IN
V
FLBK
R2
LOAD
COMP I
R1
FB
V
FB
Q1 Q2
R
CMP
C
CMP
R
SENSE
SENSE
+
42691 F11
Q3
–
+
A1
16
22 21
20
Figure 11. Load Compensation Diagram