Datasheet

LTC4269-1
34
42691fc
APPLICATIONS INFORMATION
For each secondary-side power MOSFET, the BV
DSS
should
be greater than:
BV
DSS
≥ V
OUT
+ V
IN(MAX)
• N
SP
Choose the primary-side MOSFET R
DS(ON)
at the nominal
gate drive voltage (7.5V). The secondary-side MOSFET gate
drive voltage depends on the gate drive method.
Primary-side power MOSFET RMS current is given by:
I
RMS(PRI)
=
P
IN
V
IN(MIN)
DC
MAX
For each secondary-side power MOSFET RMS current is
given by:
I
RMS(SEC)
=
I
OUT
1−DC
MAX
Calculate MOSFET power dissipation next. Because the
primary-side power MOSFET operates at high V
DS
, a
transition power loss term is included for accuracy. C
MILLER
is the most critical parameter in determining the transition
loss, but is not directly specifi ed on the data sheets.
C
MILLER
is calculated from the gate charge curve included
on most MOSFET data sheets (Figure 16).
With C
MILLER
determined, calculate the primary-side power
MOSFET power dissipation:
P
D(PRI)
=I
RMS(PRI)
2
•R
DS(ON)
1+δ
()
+
V
IN(MAX)
•
P
IN(MAX)
DC
MIN
•R
DR
•
C
MILLER
V
GATE(MAX)
− V
TH
•f
OSC
where:
R
DR
is the gate driver resistance (≈10Ω)
V
TH
is the MOSFET gate threshold voltage
f
OSC
is the operating frequency
V
GATE(MAX)
= 7.5V for this part
(1 + δ) is generally given for a MOSFET in the form of a
normalized R
DS(ON)
vs temperature curve. If you don’t have
a curve, use δ = 0.005/°C • ΔT for low voltage MOSFETs.
The secondary-side power MOSFETs typically operate
at substantially lower V
DS
, so you can neglect transition
losses. The dissipation is calculated using:
P
DIS(SEC)
= I
RMS(SEC)
2
• R
DS(ON)
(1 + δ)
With power dissipation known, the MOSFETs’ junction
temperatures are obtained from the equation:
T
J
= T
A
+ P
DIS
• θ
JA
where T
A
is the ambient temperature and θ
JA
is the MOSFET
junction to ambient thermal resistance.
Once you have T
J
iterate your calculations recomputing
δ and power dissipations until convergence.
Gate Drive Node Consideration
The PG and SG gate drivers are strong drives to minimize
gate drive rise and fall times. This improves effi ciency,
but the high frequency components of these signals can
cause problems. Keep the traces short and wide to reduce
parasitic inductance.
The parasitic inductance creates an LC tank with the
MOSFET gate capacitance. In less than ideal layouts, a
series resistance of 5Ω or more may help to dampen the
ringing at the expense of slightly slower rise and fall times
and poorer effi ciency.
The LTC4269-1 gate drives will clamp the max gate voltage
Q
A
V
GS
ab
42691 F16
Q
B
MILLER EFFECT
GATE CHARGE (Q
G
)
Figure 16. Gate Charge Curve
The fl at portion of the curve is the result of the Miller (gate
to-drain) capacitance as the drain voltage drops. The Miller
capacitance is computed as:
C
MILLER
=
Q
B
−Q
A
V
DS
The curve is done for a given V
DS
. The Miller capacitance
for different V
DS
voltages are estimated by multiplying the
computed C
MILLER
by the ratio of the application V
DS
to
the curve specifi ed V
DS
.