Datasheet

LTC4269-1
19
42691fc
reliably not only when an initially charged cable connects
and dissipates the energy through the PD front end, but
also when the electrical power system grounds are subject
to very high energy events (e.g. lightning strikes).
In these high energy events, adding 10 series resistance
into the V
PORTP
pin greatly improves the robustness of
the LTC4269-1 based PD. (See Figure 7) The TVS limits
the voltage across the port while the 10 and 0.1µF ca-
pacitance reduces the edge rate the LT4269-1 encounters
across its pin. The added10 series resistance does not
operationally affect the LTC4269-1 PD interface nor does
it affect its compliance with the IEEE802.3 standard.
Transient Voltage Suppressor
The LTC4269-1 specifi es an absolute maximum voltage of
100V and is designed to tolerate brief overvoltage events.
However, the pins that interface to the outside world can rou-
tinely see excessive peak voltages. To protect the LTC4269-
1, install a transient voltage suppressor (D3) between the
input diode bridge and the LTC4269-1 as shown in Figure 7.
A SMAJ58A is recommended for typical PD applications.
However, a SMBJ58A may be preferred in applications
where the PD front end must absorb higher energy dis-
charge events.
Classifi cation Resistor (R
CLASS
)
The R
CLASS
resistor sets the classifi cation load current, cor-
responding to the PD power classifi cation. Select the value
of R
CLASS
from Table 2 and connect the resistor between
the R
CLASS
and V
PORTN
pins as shown in Figure 4, or fl oat
the R
CLASS
pin if the classifi cation load current is not re-
quired. The resistor tolerance must be 1% or better to avoid
degrading the overall accuracy of the classifi cation circuit.
Load Capacitor
The IEEE 802.3af/at specifi cation requires that the PD
maintains a minimum load capacitance of 5F and does
not specify a maximum load capacitor. However, if the
load capacitor is too large, there may be a problem with
inadvertent power shutdown by the PSE.
This occurs when the PSE voltage drops quickly. The input
diode bridge reverses bias, and the PD load momentarily
powers off the load capacitor. If the PD does not draw
power within the PSE’s 300ms disconnection delay, the
PSE may remove power from the PD. Thus, it is necessary
to evaluate the load current and capacitance to ensure that
an inadvertent shutdown cannot occur.
The load capacitor can store signifi cant energy when fully
charged. The PD design must ensure that this energy is not
inadvertently dissipated in the LTC4269-1. For example,
if the V
PORTP
pin shorts to V
PORTN
while the capacitor
is charged, current will fl ow through the parasitic body
diode of the internal MOSFET and may cause permanent
damage to the LTC4269-1.
T2P Interface
When a 2-event classifi cation sequence successfully
completes, the LTC4269-1 recognizes this sequence,
and provides an indicator bit, declaring the presence of
a Type 2 PSE. The open-drain output provides the option
to use this signal to communicate to the LTC4269-1 load,
or to leave the pin unconnected.
Figure 8 shows two interface options using the T2P pin
and the opto-isolator. The T2P pin is active low and con-
nects to an opto-isolator to communicate across the DC/
DC converter isolation barrier. The pull-up resistor R
P
is
sized according to the requirements of the opto-isolator
APPLICATIONS INFORMATION
42691 F08
OPTION 1: SERIES CONFIGURATION FOR ACTIVE LOW/LOW IMPEDANCE OUTPUT
–54V
TO
PSE
R
P
TO PD LOAD
V
PORTP
LTC4269-1
V
PORTN
T2P
V
+
OPTION 2: SHUNT CONFIGURATION FOR ACTIVE HIGH/OPEN COLLECTOR OUTPUT
–54V
TO
PSE
R
P
TO PD LOAD
V
PORTP
LTC4269-1
V
PORTN
T2P
V
+
Figure 8. T2P Interface Examples