Datasheet

LTC4352
12
4352fa
Figure 8. Recommended PCB Layout for Power MOSFET
1 2 3 4 5 6
12 11 10
9 8 7
C1
S
S
S
G
D
D
D
D
DRAWING IS NOT TO SCALE!
VIA TO GROUND PLANE
SOURCE
GATE
LTC4352 MSOP-12
GND
OUT
V
IN
V
CC
VIA TO GROUND PLANE
CURRENT FLOWCURRENT FLOW
W W
TRACK WIDTH W:
0.03˝ PER AMPERE
ON 1OZ CU FOIL
FROM INPUT
SUPPLY
TO LOAD
Q1
SO-8
4352 F08
applicaTions inForMaTion
LEDs, D1 and D2, require around 3mA for good luminous
intensity. Accounting for a 2V diode drop and 0.5V V
OL
,
R1 and R2 are set to 2.7k.
PCB Layout Considerations
Connect the V
IN
and OUT pin traces as close as possible
to the MOSFET’s terminals. Keep the traces to the MOSFET
wide and short to minimize resistive losses. The PCB traces
associated with the power path through the MOSFET should
have low resistance. See Figure 8.
It is also important to put C1, the bypass capacitor for the
V
CC
pin, as close as possible between V
CC
and GND. Also
place C2 near the CPO and SOURCE pins. Surge suppres-
sors, when used, should be mounted close to the LTC4352
using short lead lengths.