Datasheet

QUICK START GUIDE FOR DEMONSTRATION CIRCUIT 1249
POE TO 3.3V@3.0A ISOLATED
3
level current limit. When the voltage between
POUT and VPORTN falls below the Power Good
trip point, the Power Good signal goes active low
and the amperage through the power switch is
held below the high-level current limit.
For the PD to remain powered on, it must present
to the PSE both AC and DC components of the
Maintain Power Signature (MPS). The PD must
hold the DC MPS by drawing at least 10mA or the
PSE may disconnect power. The DC1249 demo
board does implement a minimum load option with
the JP2 jumper. By enabling this jumper the the
circuit will draw approximately 16.5mA to satisfy
the DC disconnect requirements.
The synchronous Flyback converter operates at a
typical switching frequency of 300kHz, controlled
by the current mode controller portion of the
LT4267-3. Galvanic isolation is achieved through
transformer T1 and opto-isolator U4.
The primary side power path is comprised of C1,
L1, Cin1, ½ of T1, Q2, and RCS. These compo-
nents should be as close to each other as possible
when laying out the printed circuit board. The
secondary side power path is made up of the
other ½ of T1, D1, and Cox. These parts should
also be laid out as close to each other as possible,
without overlapping any of the circuitry or traces of
the primary side.
IN ORDER TO ENSURE PROPER OPERATION,
THE DESIGNER MUST ENSURE THAT THE PD
INPUT CURRENT REQUIREMENT DOES NOT
EXCEED THE LTC4267-3 CURRENT LIMIT
OVER THE UNIT’S OPERATING VOLTAGE
RANGE.