Datasheet

LTM4616
17
4616ff
For more information www.linear.com/LTM4616
applications inForMation
OUTPUT VOLTAGE (V)
TIME
MASTER OUTPUT
SLAVE OUTPUT
4616 F06
Figure 6. Output Voltage Coincident Tracking
Therefore R
TB
= 10k and R
TA
= 6.65k in Figure 5. Figure6
shows the output voltage for coincident tracking.
In ratiometric tracking, a different slew rate maybe desired
for the slave regulator. R
TB
can be solved for when SR
is slower than MR. Make sure that the slave supply slew
rate is chosen to be fast enough so that the slave output
voltage will reach it final value before the master output.
For example: MR = 3.3V/ms and SR = 1.5V/ms. Then
R
TB
= 22.1k. Solve for R
TA
to equal to 4.87k.
For applications that do not require tracking or sequencing,
simply tie the TRACK pin to SV
IN
to let RUN control the
turn on/off. Connecting TRACK to SV
IN
also enables the
~100µs of internal soft-start during start-up.
becomes high, and 3.3V output starts its shutdown after
the PGOOD signal of 1.5V output becomes low. This can
be applied to systems that require voltage sequencing
between the core and sub-power supplies. The PGOOD
pull-up resistor value can be determined as follows:
R
PGOOD(MAX)
=
SV
IN
– V
RUN
I
PGOOD(MAX)
For example: V
IN
= SV
IN
= 5V, V
RUN
= 1.7V and I
PGOOD(MAX)
= 30µA. Solve for R
PGOOD(MAX)
to equal 110k. Selecting a
value of 100k provides some margin.
Stability Compensation
The module has already been internally compensated
for all output voltages. Table 2 is provided for most ap
-
plication requirements
.
LTpowerCAD is available for fine
adjustments to the control loop.
Output Margining
For a convenient system stress test on the LTM4616’s
output, the user can program each output to ±5%, ±10%
or ±15% of its normal operational voltage. Margining
can be disabled by connecting the MGN pin to a voltage
divider as shown in Figure 5. When the MGN pin is <0.3V,
it forces negative margining, in which the output voltage
is below the regulation point. When MGN is >V
IN
– 0.3V,
the output voltage is forced above the regulation point.
The MGN pin with a voltage divider is driven with a small
tri-state gate as shown in Figure 18 for three margin states,
(High, Low, and No Margin). The amount of output voltage
margining is determined by the BSEL pin. When BSEL is
low, it’s 5%. When BSEL is high, it’s 10%. When BSEL is
floating, it’s 15%. When margining is active
, the internal
output
overvoltage and undervoltage comparators are
disabled and PGOOD remains high.
Power Good
The PGOOD pin is an open-drain pin that can be used to
monitor valid output voltage regulation. This pin monitors
a ±10% window around the regulation point. As shown
in Figure 20, the sequencing function can be realized in a
dual output application by controlling the RUN pins and the
PGOOD signals from each other. The 1.5V output begins
its soft starting after the PGOOD signal of 3.3V output