Datasheet

LTC4357
8
4357fd
Design Example
The following design example demonstrates the calcula-
tions involved for selecting components in a 12V system
with 10A maximum load current (see Figure 4).
First, calculate the R
DS(ON)
of the MOSFET to achieve the de-
sired forward drop at full load. Assuming V
DROP
= 0.1V,
R
DS(ON)
≤
V
DROP
I
LOAD
=
0.1V
10A
R
DS(ON)
≤ 10mΩ
The Si4874DY offers a good solution, in an S8 package
with R
DS(ON)
= 10mΩ(max) and BV
DSS
of 30V.
The maximum power dissipation in the MOSFET is:
P = I
LOAD
2
• R
DS(ON)
= (10A)
2
• 10mΩ = 1W
With less than 39µF of local bypass, the recommended RC
values of 100Ω and 0.1µF were used in Figure 4.
Since BV
DSS
+ V
IN
is much less than 100V, output clamp-
ing is unnecessary.
Figure 3. Protecting Against Collapse of V
DD
During Reverse Recovery
applications inForMation
Figure 2. Reverse Recovery Produces Inductive Spikes at the IN and OUT Pin.
The Polarity of Step Recovery Spikes is Shown Across Parasitic Inductances
4357 F02
LTC4357
+ –
GND
IN OUT
V
DD
GATE
M1
REVERSE RECOVERY CURRENT
V
IN
INPUT
SHORT
D
IN
SBR1U-
150SA
INPUT PARASITIC
INDUCTANCE
C
OUT
10µF
V
OUT
C
LOAD
D
CLAMP
SMAT70A
OR
+ –
OUTPUT PARASITIC
INDUCTANCE
4357 F03
LTC4357
GND
IN OUT
V
DD
GATE
M1
OUTPUT PARASITIC
INDUCTANCE
V
IN
R1
100Ω
C1
100nF
INPUT
SHORT
C
OUT
V
OUT
C
LOAD
OR
Figure 4. 12V, 10A Diode-OR
4357 F04
LTC4357
GND
IN OUT
V
DD
GATE
M2
Si4874DY
V
IN2
12V
R1
100Ω
C1
0.1µF
R1
100Ω
C1
0.1µF
LTC4357
GND
IN OUT
V
DD
GATE
M1
Si4874DY
V
IN1
12V
V
OUT
TO LOAD