Datasheet
LTC2365/LTC2366
20
23656fb
For more information www.linear.com/LTC2365
applications inForMation
BOARD LAYOUT AND BYPASSING
Wire wrap boards are not recommended for high resolu-
tion and/or high speed A/D converters. To obtain the best
performance from the LTC2365/LTC2366, a printed circuit
board with ground plane is required. Layout for the printed
circuit board should ensure that digital and analog signal
lines are separated as much as possible. In particular, care
should be taken not to run any digital track alongside an
analog signal track or underneath the ADC. The analog
input should be screened by the ground plane.
High quality tantalum and ceramic bypass capacitors
should be used at the V
DD
and V
REF
pins as shown in the
Typical Application circuit on the first page of this data
sheet. For optimum performance, a 10µF surface mount
AVX capacitor with a 0.1µF ceramic is recommended for
the V
DD
pin and a 4.7µF surface mount AVX capacitor
with a 0.1µF ceramic is recommended for the V
REF
and
OV
DD
pins. Alternatively, 4.7µF and 10µF ceramic chip
capacitors such as Murata GRM235Y5V106Z016 may
be used. The capacitors must be located as close to the
pins as possible. The traces connecting the pins and the
bypass capacitors must be kept short and should be made
as wide as possible.
Figure 20 shows the recommended system ground con-
nections. All analog circuitry grounds should be terminated
at the LTC2365/LTC2366. The ground return from the
LTC2365/LTC2366 to the power supply should be low
impedance for noise free operation. Digital circuitry
grounds must be connected to the digital supply
common.
In applications where the ADC data outputs and control
signals are connected to a continuously active micropro-
cessor bus, it is possible to get errors in the conversion
results. These errors are due to feedthrough from the
microprocessor to the successive approximation com-
parator. The problem can be eliminated by forcing the
microprocessor into a Wait state during conversion or
by using three-state buffers to isolate the ADC data bus.
Figure 20. Power Supply Ground Practice
23656 F20
GND
A
IN
V
DD
CA
IN
CS
SDO
SCK
CV
DD
PIN 1
VIAS TO GROUND PLANE
+
10µF