Datasheet

LTC2308
9
2308fb
TEST CIRCUIT
SDO
3k
C
L
V
DD
TEST POINT
2308 TC01
Load Circuit for t
dis
WAVEFORM 2, t
en
Load Circuit for t
dis
WAVEFORM 1
SDO
3k
TEST POINT
2308 TC02
C
L
TIMING DIAGRAM
SCK
SDO
V
IL
t
dDO
t
hDO
V
OH
V
OL
2308 TD01
2308 TD04
CONVST
SDO
t
en
SDO
t
r
t
f
2308 TD05
V
OH
V
OL
SDO
WAVEFORM 1
(SEE NOTE 1)
V
IH
t
dis
90%
10%
SDO
WAVEFORM 2
(SEE NOTE 2)
CONVST
NOTE 1: WAVEFORM 1 IS FOR AN OUTPUT WITH INTERNAL CONDITIONS SUCH
THAT THE OUTPUT IS HIGH UNLESS DISABLED BY THE OUTPUT CONTROL
NOTE 2: WAVEFORM 2 IS FOR AN OUTPUT WITH INTERNAL CONDITIONS SUCH
THAT THE OUTPUT IS LOW UNLESS DISABLED BY THE OUTPUT CONTROL
2308 TD02
2308 TD03
SCK
SDI
t
WLCLK
t
WHCLK
t
HD
t
SUDI
Voltage Waveforms for SDO Delay Times, t
dDO
and t
hDO
Voltage Waveforms for t
dis
Voltage Waveforms for SDO Rise and Fall Times t
r
, t
f
Voltage Waveforms for t
en
t
WLCLK
(SCK Low Time)
t
WHCLK
(SCK High Time)
t
HD
(Hold Time SDI After SCK↑)
t
SUDI
(Setup Time SDI Stable Before SCK↑)