Datasheet

LTC2308
10
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APPLICATIONS INFORMATION
Overview
The LTC2308 is a low noise, 500ksps, 8-channel, 12-bit
successive approximation register (SAR) A/D converter.
The LTC2308 includes a precision internal reference, a
confi gurable 8-channel analog input multiplexer (MUX)
and an SPI-compatible serial port for easy data transfers.
The ADC may be confi gured to accept single-ended or
differential signals and can operate in either unipolar or
bipolar mode. A sleep mode option is also provided to
save power during inactive periods.
Conversions are initiated by a rising edge on the CONVST
input. Once a conversion cycle has begun, it cannot be
restarted. Between conversions, a 6-bit input word (D
IN
)
at the SDI input confi gures the MUX and programs vari-
ous modes of operation. As the D
IN
bits are shifted in,
data from the previous conversion is shifted out on SDO.
After the 6 bits of the D
IN
word have been shifted in, the
ADC begins acquiring the analog input in preparation for
the next conversion as the rest of the data is shifted out.
The acquire phase requires a minimum time of 240ns
for the sample-and-hold capacitors to acquire the analog
input signal.
During the conversion, the internal 12-bit capacitive
charge-redistribution DAC output is sequenced through a
successive approximation algorithm by the SAR starting
from the most signifi cant bit (MSB) to the least signifi cant
bit (LSB). The sampled input is successively compared
with binary weighted charges supplied by the capacitive
DAC using a differential comparator. At the end of a conver-
sion, the DAC output balances the analog input. The SAR
contents (a 12-bit data word) that represent the sampled
analog input are loaded into 12 output latches that allow
the data to be shifted out.
Programming the LTC2308
The various modes of operation of the LTC2308 are
programmed by a 6-bit D
IN
word. The SDI data bits are
loaded on the rising edge of SCK, with the S/D bit loaded
on the fi rst rising edge and the SLP bit on the sixth rising
edge (see Figure 8 in the Timing and Control section). The
input data word is defi ned as follows:
S/D = SINGLE-ENDED/DIFFERENTIAL BIT
O/S = ODD/SIGN BIT
S1 = ADDRESS SELECT BIT 1
S0 = ADDRESS SELECT BIT 0
UNI = UNIPOLAR/BIPOLAR BIT
SLP = SLEEP MODE BIT
Analog Input Multiplexer
The analog input MUX is programmed by the S/D, O/S,
S1 and S0 bits of the D
IN
word. Table 1 lists the MUX
confi gurations for all combinations of the confi guration
bits. Figure 1a shows several possible MUX confi gurations
and Figure 1b shows how the MUX can be reconfi gured
from one conversion to the next.
S/D O/S S1 S0 UNI SLP
Table 1. Channel Confi guration
S/DO/SS1S001234567COM
0000+–
0001 +–
0010 +–
0011 +–
0100–+
0101 –+
0110 –+
0111 –+
1000+ –
1001 + –
1010 + –
1011 + –
1100 + –
1101 + –
1110 + –
1111 + –