Datasheet

LTC4267
4
4267fc
The ● denotes the specifi cations which apply over the full operating
temperature range, otherwise specifi cations are at T
A
= 25°C. (Note 3)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
t
RISE
NGATE Drive Rise Time C
LOAD
= 3000pF, P
VCC
– P
GND
= 8V 40 ns
t
FALL
NGATE Drive Fall Time C
LOAD
= 3000pF, P
VCC
– P
GND
= 8V 40 ns
V
IMAX
Peak Current Sense Voltage R
SL
= 0, P
VCC
– P
GND
= 8V (Note 16) ● 90 100 115 mV
I
SLMAX
Peak Slope Compensation Output Current P
VCC
– P
GND
= 8V (Note 17) 5 µA
t
SFST
Soft-Start Time P
VCC
– P
GND
= 8V 1.4 ms
T
SHUTDOWN
Thermal Shutdown Trip Temperature (Notes 14, 18) 140 °C
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: P
VCC
internal clamp circuit self regulates to 9.4V with respect to
PGND.
Note 3: The LTC4267 operates with a negative supply voltage in the range
of – 1.5V to – 57V. To avoid confusion, voltages for the PD interface
are always referred to in terms of absolute magnitude. Terms such as
“maximum negative voltage” refer to the largest negative voltage and
a “rising negative voltage” refers to a voltage that is becoming more
negative.
Note 4: The LTC4267 is designed to work with two polarity protection
diode drops between the PSE and PD. Parameter ranges specifi ed in the
Electrical Characteristics section are with respect to this product pins and
are designed to meet IEEE 802.3af specifi cations when these diode drops
are included. See the Application Information section.
Note 5: Signature resistance is measured via the two-point ΔV/ΔI method
as defi ned by IEEE 802.3af. The PD signature resistance is offset from the
25kΩ to account for diode resistance. With two series diodes, the total PD
resistance will be between 23.75kΩ and 26.25kΩ and meet IEEE 802.3af
specifi cations. The minimum probe voltages measured at the LTC4267
pins are –1.5V and –2.5V. The maximum probe voltages are –8.5V and
–9.5V.
Note 6: The PD interface includes hysteresis in the UVLO voltages to
preclude any start-up oscillation. Per IEEE 802.3af requirements, the PD
will power up from a voltage source with 20Ω series resistance on the fi rst
trial.
Note 7: Dynamic Supply current is higher due to the gate charge being
delivered at the switching frequency.
Note 8: I
VPORTN_CLASS
does not include classifi cation current
programmed at the R
CLASS
pin. Total current in classifi cation mode will be
I
VPORTN_CLASS
+ I
CLASS
(See note 9).
Note 9: I
CLASS
is the measured current fl owing through R
CLASS
. ΔI
CLASS
accuracy is with respect to the ideal current defi ned as I
CLASS
= 1.237/
R
CLASS
. The current accuracy does not include variations in R
CLASS
resistance. The total classifi cation current for a PD also includes the IC
quiescent current (I
VPORTN_CLASS
). See Applications Information.
Note 10: For the DHC package, this parameter is assured by design and
wafer level testing.
Note 11: To disable the 25kΩ signature, tie SIGDISA to V
PORTP
or hold
SIGDISA high with respect to V
PORTN
. See Applications Information.
Note 12: The switching regulator is tested in a feedback loop that servos
V
FB
to the output of the error amplifi er while maintaining I
TH
/RUN at the
midpoint of the current limit range.
Note 13: I
POUT_LEAK
includes current drawn through P
OUT
by the power
good status circuit. This current is compensated for in the 25kΩ signature
resistance and does not affect PD operation.
Note 14: The LTC4267 PD Interface includes thermal protection. In the
event of an overtemperature condition, the PD interface will turn off
the switching regulator until the part cools below the overtemperature
limit. The LTC4267 is also protected against thermal damage from
incorrect classifi cation probing by the PSE. If the LTC4267 exceeds the
overtemperature threshold, the classifi cation load current is disabled.
Note 15: The PD interface includes dual level input current limit. At turn-
on, before the P
OUT
load capacitor is charged, the PD current level is set
to a low level. After the load capacitor is charged and the P
OUT
– V
PORTN
voltage difference is below the power good threshold, the PD switches to
high level current limit. The PD stays in high level current limit until the
input voltage drops below the UVLO turn-off threshold.
Note 16: Peak current sense voltage is reduced dependent on duty cycle
and an optional external resistor in series with the SENSE pin (R
SL
). For
details, refer to the programmable slope compensation feature in the
Applications Information section.
Note 17: Guaranteed by design.
Note 18: The PD interface includes overtemperature protection that is
intended to protect the device from momentary overload conditions.
Junction temperature will exceed 125°C when overtemperature protection
is active. Continuous operation above the specifi ed maximum operating
junction temperature may impair device reliability.
ELECTRICAL CHARACTERISTICS