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LTC2751

2751fa

150pF

–

1/2 LT

1469

–

1/2 LT1469

16-BIT DAC WITH SPAN SELECT

LTC2751-16

VOS

COM

R2R1

OFS

REF

OUT1

OUT

OUT2

GND

UPD

READ

D/S

CLR

MSPAN

SPAN I/O

S2-S0

15pF

2751 TA01

UPD

READ

D/S

CLR

0.1µF

DATA I/O

D15-D0

Typical applicaTion

FeaTures

applicaTions

DescripTion

Current Output

12-/14-/16-Bit SoftSpan

DACs with Parallel I/O

The LTC

2751 is a family of 12-, 14-, and 16-bit multi-

plying parallel-input, current-output DACs. They operate

from a single 2.7V to 5.5V supply. All parts are guaranteed

monotonic over temperature. The LTC2751A-16 provides

16-bit performance (±1LSB INL and DNL) over temperature

without any adjustments. These SoftSpan™ DACs offer six

output ranges—two unipolar and four bipolar—that can be

programmed through the parallel interface, or pinstrapped

for operation in a single range.

These parts use a bidirectional input/output parallel in-

terface that allows readback of any on-chip register. A

power-on circuit resets the DAC output to 0V when power is

initially applied. A logic low on the CLR pin asynchronously

clears the DAC to 0V in any output range.

The parts are specified over commercial and industrial

temperature ranges.

L, LT, LTC, LTM , Linear Technology and the Linear logo are registered trademarks and

SoftSpan is a trademark of Linear Technology Corporation. All other trademarks are the property

of their respective owners.

16-Bit DAC with Software Selectable Ranges

Six Programmable Output Ranges

Unipolar: 0V to 5V, 0V to 10V

Bipolar: ±5V, ±10V, ±2.5V, –2.5V to 7.5V

Maximum 16-Bit INL Error: ±1 LSB over Temperature

Low 1µA (Maximum) Supply Current

Guaranteed Monotonic over Temperature

Low Glitch Impulse 1nV • s

2.7V to 5.5V Single Supply Operation

2µs Settling Time to ±1 LSB

Reference Input: ±15V

Parallel Interface with Readback of All Registers

Asynchronous CLR Pin Clears DAC Output to 0V in

Any Output Range

Power-On Reset to 0V

38-Pin 5mm × 7mm QFN Package

High Resolution Offset and Gain Adjustment

Process Control and Industrial Automation

Automatic Test Equipment

Data Acquisition Systems

LTC2751-16 Integral Nonlinearity

CODE

–1.0

INL (LSB)

–0.8

–0.4

–0.2

0.0

1.0

0.4

16384

32768

–0.6

0.6

0.8

0.2

49152

65535

2751 TA01b

25°C

90°C

–45°C

= 5V

REF

= 5V

±10V RANGE

Summary of content (22 pages)

PAGE 1
LTC2751 Current Output 12-/14-/16-Bit SoftSpan DACs with Parallel I/O Features Description Six Programmable Output Ranges Unipolar: 0V to 5V, 0V to 10V Bipolar: ±5V, ±10V, ±2.5V, –2.5V to 7.5V n Maximum 16-Bit INL Error: ±1 LSB over Temperature n Low 1µA (Maximum) Supply Current n Guaranteed Monotonic over Temperature n Low Glitch Impulse 1nV • s n 2.7V to 5.
PAGE 2
LTC2751 Absolute Maximum Ratings (Notes 1, 2) Operating Temperature Range LTC2751C...................................................... 0°C to 70°C LTC2751I...................................................–40°C to 85°C Maximum Junction Temperature........................... 125°C Storage Temperature Range................... –65°C to 150°C IOUT1, IOUT2, RCOM to GND......................................±0.3V RFB, ROFS, RIN, REF, RVOS to GND............................ ±15V VDD to GND....................
PAGE 3
LTC2751 Electrical Characteristics VDD = 5V, VREF = 5V unless otherwise specified. The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. LTC2751-12 SYMBOL PARAMETER CONDITIONS MIN TYP MAX LTC2751-14 MIN TYP LTC2751B-16 MAX MIN TYP MAX LTC2751A-16 MIN TYP MAX UNITS Static Performance Resolution l 12 12 14 16 14 16 16 Bits 16 Bits Monotonicity l DNL Differential Nonlinearity l ±1 ±1 ±1 ±0.
PAGE 4
LTC2751 Electrical Characteristics VDD = 5V, VREF = 5V unless otherwise specified. The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS VIH Digital Input High Voltage 3.3V ≤ VDD ≤ 5.5V 2.7V ≤ VDD < 3.3V l l VIL Digital Input Low Voltage 4.5V < VDD ≤ 5.5V 2.7V ≤ VDD ≤ 4.5V l l 0.8 0.
PAGE 5
LTC2751 timing Characteristics VDD = 5V, VREF = 5V unless otherwise specified. The l denotes specifications that apply over the full operating temperature range, otherwise specifications are at TA = 25°C. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS VDD = 2.7V to 3.
PAGE 6
LTC2751 Typical Performance Characteristics TA = 25°C, unless otherwise noted. LTC2751-16 Integral Nonlinearity (INL) Differential Nonlinearity (DNL) 1.0 1.0 VDD = 5V 0.8 VREF = 5V ±10V RANGE 0.6 0.4 0.4 0.2 0.2 DNL (LSB) INL (LSB) VDD = 5V 0.8 VREF = 5V ±10V RANGE 0.6 0.0 –0.2 0.0 –0.2 –0.4 –0.4 –0.6 –0.6 – 0.8 –0.8 –1.0 0 16384 32768 CODE –1.0 65535 49152 16384 0 32768 CODE 2751 G01 INL vs Temperature 0.2 0.0 –0.4 –0.6 –0.6 – 0.8 –0.8 80 –DNL –1.
PAGE 7
LTC2751 Typical Performance Characteristics TA = 25°C, unless otherwise noted. LTC2751-16 INL vs VDD Settling 0V to 10V 1.0 0.8 UPD 5V/DIV 0.6 INL (LSB) 0.4 +INL 0.2 0.0 GATED SETTLING WAVEFORM 250µV/DIV –INL –0.2 –0.4 –0.6 –1.0 2.5 3 3.5 4 4.5 VDD (V) 5 2751 G10 500ns/DIV USING LT1469 AMP CFEEDBACK = 12pF 0V TO 10V STEP – 0.8 5.5 2751 G09b LTC2751-14 Integral Nonlinearity (INL) Differential Nonlinearity (DNL) 1.0 1.0 VDD = 5V 0.8 VREF = 5V ±10V RANGE 0.6 0.4 0.4 0.2 0.
PAGE 8
LTC2751 Typical Performance Characteristics LTC2751-12, LTC2751-14, LTC2751-16 TA = 25°C, unless otherwise noted.
PAGE 9
LTC2751 Pin Functions RCOM (Pin 1): Center Tap Point of RIN and REF. Normally tied to the negative input of the external reference inverting amplifier. RIN (Pin 2): Input Resistor for External Reference Inverting Amplifier. Normally tied to the external reference voltage VREF and to ROFS (Pin 37). Typically 5V; accepts up to ±15V. S2 (Pin 3): Span I/O Bit 2. Pins S0, S1 and S2 are used to program and to read back the output range of the DAC. IOUT2 (Pin 4): DAC Current Output Complement. Tie IOUT2 to GND.
PAGE 10
LTC2751 Pin Functions S1 (Pin 33): Span I/O Bit 1. Pins S0, S1 and S2 are used to program and to read back the output range of the DAC. RVOS (Pin 34): DAC Offset Adjust. Nominal input range is ±5V. If not used, RVOS should be shorted to IOUT2 . IOUT1 (Pin 35): DAC current output; normally tied to the negative input of the I/V converter amplifier. RFB (Pin 36): DAC Feedback Resistor; normally tied to the output of the I/V converter amplifier.
PAGE 11
LTC2751 Block Diagram 1 RIN 2 38 RCOM R1 READ 37 REF ROFS 36 RFB R2 IOUT1 16-BIT DAC WITH SPAN SELECT 29 WR 3 31 IOUT2 35 4 16 UPD 30 D/S 28 CONTROL LOGIC DAC REGISTER 3 DAC REGISTER 16 CLR 17 MSPAN INPUT REGISTER INPUT REGISTER I/O PORT I/O PORT 18 3 16 3, 32, 33 6-14, 19-25 SPAN I/O S2-S0 2751 BD DATA I/O D15-D0 2751fa 11
PAGE 12
LTC2751 Timing Diagrams Write, Update and Clear Timing t3 t1 WR t2 I/O INPUT t5 UPD t6 t4 t7 t8 D/S t25 CLR 2751 TD01 Readback Timing READ WR t14 t13 t23 t24 I/O INPUT t15 I/O OUTPUT t17 t19 t20 t22 UPD t18 D/S 2751 TD02 Operation Output Ranges Digital Section The LTC2751 is a current-output, parallel-input precision multiplying DAC with software-programmable output ranges. SoftSpan provides two unipolar output ranges (0V to 5V and 0V to 10V), and four bipolar ranges (±2.
PAGE 13
LTC2751 Operation Write and Update Operations Table 1 shows the functions of the LTC2751. The data input register is loaded directly from a 16-bit microprocessor bus by holding the D/S pin low and then pulsing the WR pin low. The second register (DAC register) is loaded by pulsing the UPD pin high, which copies the data held in the input register into the DAC register.
PAGE 14
LTC2751 Operation Table 2. Span Codes S2 S1 S0 SPAN 0 0 0 Unipolar 0V to 5V 0 0 1 Unipolar 0V to 10V 0 1 0 Bipolar –5V to 5V 0 1 1 Bipolar –10V to 10V 1 0 0 Bipolar –2.5V to 2.5V 1 0 1 Bipolar –2.5V to 7.5V Codes not shown are reserved and should not be used. Readback The contents of any one of the four interface registers can be read back by using the READ pin in conjunction with the D/S and UPD pins. A readback operation is initiated by bringing READ to logic high.
PAGE 15
LTC2751 Operation—Examples 1. Load ±5V range with the output at 0V. Note that since span and code are updated together, the output, if started at 0V, will stay there. WR SPAN I/O INPUT 010 DATA I/O INPUT 8000 H UPD UPDATE (5V RANGE, VOUT = 0V) D/S READ = LOW 2751 TD03 2. Load ±10V range with the output at 5V, changing to –5V. WR SPAN I/O INPUT DATA I/O INPUT 011 C000 H 4000 H UPD UPDATE (5V) UPDATE (–5V) D/S READ = LOW 2751 TD04 3.
PAGE 16
LTC2751 Applications Information Op Amp Selection when programmed in a unipolar or bipolar output range. These are the changes the op amp can cause to the INL, DNL, unipolar offset, unipolar gain error, bipolar zero and bipolar gain error. Tables 3 and 4 can also be used to determine the effects of op amp parameters on the LTC2751-14 and the LTC2751-12. However, the results obtained from Tables 3 and 4 are in 16-bit LSBs.
PAGE 17
LTC2751 Applications Information Op amp offset will contribute mostly to output offset and gain error and has minimal effect on INL and DNL. For the LTC2751-16, a 250µV op amp offset will cause about 0.8LSB INL degradation and 0.2LSB DNL degradation with a 5V reference. For the LTC2751 programmed in 5V unipolar mode, the same 250µV op amp offset will cause a 3.3LSB zero-scale error and a 3.3LSB gain error.
PAGE 18
LTC2751 Applications Information ALTERNATE AMPLIFIER FOR OPTIMUM SETTLING TIME PERFORMANCE 6 3 6 IOUT2 3 LT1001 + + 2 1000pF LT1468 ZETEX BAT54S 200Ω 200Ω – 6 1 2 – IOUT2 1 REF 5V 5 6 2 RIN R1 WR UPD READ D/S CLR 30 29 + 1/2 LT®1469 2 7 C2** 150pF – 1 RCOM 28 17 18 3 *SCHOTTKY BARRIER DIODE 37 36 REF ROFS RFB 38 R2 C1 15pF 15V 0.
PAGE 19
LTC2751 Typical Applications 16-Bit DAC with Software-Selectable Ranges REF 5V 5 6 2 RIN R1 + 1/2 LT1469 7 C2** 150pF – 1 RCOM 37 36 REF ROFS RFB 38 R2 LTC2751-16 WR UPD READ D/S CLR 31 30 29 28 17 18 C1 15pF IOUT1 35 WR UPD 16-BIT DAC WITH SPAN SELECT IOUT2 4 READ GND D/S CLR 3 16 MSPAN RVOS 3, 33, 32 SPAN I/O S2-S0 6-14, 19-25 DATA I/O D15-D0 34 VDD 2 – 3 + 15V 8 0.1µF 1 1/2 LT1469 16 15 C3 0.1µF VOUT 4 –15V 0.
PAGE 20
LTC2751 Package Description UHF Package 38-Lead Plastic QFN (5mm × 7mm) (Reference LTC DWG # 05-08-1701 Rev C) 0.70 ±0.05 5.50 ±0.05 5.15 ±0.05 4.10 ±0.05 3.00 REF 3.15 ±0.05 PACKAGE OUTLINE 0.25 ±0.05 0.50 BSC 5.5 REF 6.10 ±0.05 7.50 ±0.05 RECOMMENDED SOLDER PAD LAYOUT APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED 5.00 ±0.10 0.75 ±0.05 PIN 1 NOTCH R = 0.30 TYP OR 0.35 × 45° CHAMFER 3.00 REF 37 0.00 – 0.05 38 0.40 ±0.10 PIN 1 TOP MARK (SEE NOTE 6) 1 2 5.15 ±0.10 5.50 REF 7.00 ±0.10 3.
PAGE 21
LTC2751 Revision History REV DATE DESCRIPTION A 11/12 Correction made in the Typical Application diagram. PAGE NUMBER 1, 18 2751fa Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
PAGE 22
LTC2751 Typical Application Offset and Gain Trim Circuits. Powering VDD from LT1027 Ensures Quiet Supply V+ 2 IN C20 10µF U3 OUT 6 LT1027 TRIM 5 GND 4 2 1 R2 10k C13 10µF 2 GND GND C23 0.1µF C22 0.