Datasheet

LTM4602
9
4602fa
voltage V
OUT
needs to be margined up/down by ±M%,
the resistor values of R
UP
and R
DOWN
can be calculated
from the following equations:
(R
SET
R
UP
)•V
OUT
•(1+ M%)
(R
SET
R
UP
)+ 100k
= 0.6V
R
SET
•V
OUT
•(1–M%)
R
SET
+ (100k R
DOWN
)
= 0.6V
Input Capacitors
The LTM4602 μModule should be connected to a low
AC-impedance DC source. High frequency, low ESR input
capacitors are required to be placed adjacent to the mod-
ule. In Figure 21, the bulk input capacitor C
IN
is selected
for its ability to handle the large RMS current into the
converter. For a buck converter, the switching duty cycle
can be estimated as:
D=
V
OUT
V
IN
Without considering the inductor current ripple, the RMS
current of the input capacitor can be estimated as:
I
CIN(R M S)
=
I
OUT(MAX)
%
•D•(1 D)
In the above equation, η% is the estimated effi ciency of
the power module. C1 can be a switcher-rated electrolytic
aluminum capacitor, OS-CON capacitor or high volume
ceramic capacitors. Note the capacitor ripple current
ratings are often based on only 2000 hours of life. This
makes it advisable to properly derate the input capacitor,
or choose a capacitor rated at a higher temperature than
required. Always contact the capacitor manufacturer for
derating requirements.
In Figure 21, the input capacitors are used as high frequency
input decoupling capacitors. In a typical 6A output applica-
tion, 1-2 pieces of very low ESR X5R or X7R, 10μF ceramic
capacitors are recommended. This decoupling capacitor
should be placed directly adjacent the module input pins
in the PCB layout to minimize the trace inductance and
high frequency AC noise.
The typical LTM4602 application circuit is shown in Fig-
ure 21. External component selection is primarily deter-
mined by the maximum load current and output voltage.
Output Voltage Programming and Margining
The PWM controller of the LTM4602 has an internal
0.6V reference voltage. As shown in the block diagram,
a 100k/0.5% internal feedback resistor connects V
OUT
and V
OSET
pins. Adding a resistor R
SET
from V
OSET
pin to
SGND pin programs the output voltage:
V
OUT
= 0.6V •
100k + R
SET
R
SET
Table 1 shows the standard values of 1% R
SET
resistor
for typical output voltages:
Table 1
R
SET
(kΩ)
Open 100 66.5 49.9 43.2 31.6 22.1 13.7
V
OUT
(V)
0.6 1.2 1.5 1.8 2 2.5 3.3 5
Voltage margining is the dynamic adjustment of the output
voltage to its worst case operating range in production
testing to stress the load circuitry, verify control/protec-
tion functionality of the board and improve the system
reliability. Figure 2 shows how to implement margining
function with the LTM4602. In addition to the feedback
resistor R
SET
, several external components are added.
Turn off both transistor Q
UP
and Q
DOWN
to disable the
margining. When Q
UP
is on and Q
DOWN
is off, the output
voltage is margined up. The output voltage is margined
down when Q
DOWN
is on and Q
UP
is off. If the output
Figure 2. LTM4602 Margining Implementation
PGND SGND
4602 F02
LTM4602
V
OUT
V
OSET
R
SET
R
UP
Q
UP
100k
2N7002
R
DOWN
Q
DOWN
2N7002
APPLICATIONS INFORMATION