Datasheet

LTM4603HV
8
4603hvf
SI PLIFIED
W
BLOCK DIAGRA
W
Figure 1. Simplifi ed LTM4603HV Block Diagram
MARG0 (Pin C12): This pin is the LSB logic input for the
margining function. Together with the MARG1 pin will
determine if margin high, margin low or no margin state
is applied. The pin has an internal pull-down resistor of
50k. See Applications Information.
MARG1 (Pin D12): This pin is the MSB logic input for the
margining function. Together with the MARG0 pin will
determine if margin high, margin low or no margin state
is applied. The pin has an internal pull-down resistor of
50k. See Applications Information.
SGND (Pin H12): Signal Ground. This pin connects to
PGND at output capacitor point.
COMP (Pin A11): Current Control Threshold and Error
Amplifi er Compensation Point. The current comparator
threshold increases with this control voltage. The voltage
ranges from 0V to 2.4V with 0.7V corresponding to zero
sense voltage (zero current).
PGOOD (Pin G12): Output Voltage Power Good Indicator.
Open-drain logic output that is pulled to ground when the
output voltage is not within ±10% of the regulation point,
after a 25μs power bad mask timer expires.
RUN (Pin A10): Run Control Pin. A voltage above 1.9V
will turn on the module, and when below 1.9V, will turn
off the module. A programmable UVLO function can be
accomplished with a resistor from V
IN
to this pin that has
a 5.1V zener to ground. Maximum pin voltage is 5V.
V
OUT_LCL
(Pin L12): V
OUT
connects directly to this pin to
bypass the remote sense amplifi er, or DIFFV
OUT
connects
to this pin when remote sense amplifi er is used.
PI FU CTIO S
UUU
(See Package Description for Pin Assignment)
+
INTERNAL
COMP
SGND
COMP
PGOOD
RUN
V
OUT_LCL
>2V = ON
<0.9V = OFF
MAX = 5V
MARG1
MARG0
MPGM
PLLIN
C
SS
INTV
CC
DRV
CC
TRACK/SS
V
FB
f
SET
50k
33.2k
R
FB
19.1k
50k
60.4k
V
OUT
1M
5.1V
ZENER
POWER CONTROL
Q1
V
IN
4.5V TO 28V
V
OUT
2.5V
6A
Q2
10k
10k
10k
50k
10k
INTV
CC
+
–
22μF
1.5μF
C
IN
+
C
OUT
PGND
V
OSNS
–
V
OSNS
+
DIFFV
OUT
4603HV F01
4.7μF