Datasheet

LTM4603HV
7
4603hvf
PI FU CTIO S
UUU
(See Package Description for Pin Assignment)
V
IN
(Bank 1): Power Input Pins. Apply input voltage be-
tween these pins and PGND pins. Recommend placing
input decoupling capacitance directly between V
IN
pins
and PGND pins.
V
OUT
(Bank 3): Power Output Pins. Apply output load
between these pins and PGND pins. Recommend placing
output decoupling capacitance directly between these pins
and PGND pins. Review the fi gure below.
PGND (Bank 2): Power ground pins for both input and
output returns.
V
OSNS
–
(Pin M12): (–) Input to the Remote Sense Amplifi er.
This pin connects to the ground remote sense point. The
remote sense amplifi er is used for V
OUT
≤3.3V.
V
OSNS
+
(Pin J12): (+) Input to the Remote Sense Amplifi er.
This pin connects to the output remote sense point. The
remote sense amplifi er is used for V
OUT
≤3.3V.
DIFFV
OUT
(Pin K12): Output of the Remote Sense Ampli-
fi er. This pin connects to the V
OUT_LCL
pin.
DRV
CC
(Pin E12): This pin normally connects to INTV
CC
for powering the internal MOSFET drivers. This pin can
be biased up to 6V from an external supply with about
50mA capability, or an external circuit shown in Figure
16. This improves effi ciency at the higher input voltages
by reducing power dissipation in the modules.
INTV
CC
(Pin A7): This pin is for additional decoupling of
the 5V internal regulator.
PLLIN (Pin A8): External Clock Synchronization Input to
the Phase Detector. This pin is internally terminated to
SGND with a 50k resistor. Apply a clock above 2V and
below INTV
CC
. See Applications Information.
TRACK/SS (Pin A9): Output Voltage Tracking and Soft-
Start Pin. When the module is confi gured as a master
output, then a soft-start capacitor is placed on this pin
to ground to control the master ramp rate. A soft-start
capacitor can be used for soft-start turn on as a stand
alone regulator. Slave operation is performed by putting
a resistor divider from the master output to the ground,
and connecting the center point of the divider to this pin.
See Applications Information.
MPGM (Pin A12): Programmable Margining Input. A re-
sistor from this pin to ground sets a current that is equal
to 1.18V/R. This current multiplied by 10kΩ will equal a
value in millivolts that is a percentage of the 0.6V refer-
ence voltage. See Applications Information. To parallel
LTM4603HVs, each requires an individual MPGM resistor.
Do not tie MPGM pins together.
f
SET
(Pin B12): Frequency Set Internally to 1MHz. An
external resistor can be placed from this pin to ground
to increase frequency. This pin can be decoupled with a
1000pF capacitor. See Applications Information for fre-
quency adjustment.
V
FB
(Pin F12): The Negative Input of the Error Ampli-
fi er. Internally, this pin is connected to V
OUT_LCL
with a
60.4k precision resistor. Different output voltages can be
programmed with an additional resistor between V
FB
and
SGND pins. See Applications Information.
MARG1
DRV
CC
V
FB
PGOOD
SGND
V
OSNS
+
DIFFV
OUT
V
OUT_LCL
V
OSNS
–
V
IN
BANK 1
PGND
BANK 2
A
B
C
D
E
F
G
H
J
K
L
M
V
OUT
BANK 3
f
SET
MARG0
RUN COMP MPGM PLLIN INTV
CC
TRACK/SS
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